Nano-CMOS gate dielectric engineering

 Content: Machine generated contents note: 1.Overview of CMOS Technology --
 1.1.Introduction --
 1.2.MOS Transistor: A Quick Introduction to Classical Models --
 1.2.1.Current-Voltage Characteristics --
 1.2.2.Threshold Voltage --
 1.3.Short-Channel Effects and Short-Channel Modifications --
 1.3.1.Effect on I-V Characteristics --
 1.3.2.Subthreshold Conduction --
 1.3.3.Short-Channel Effects --
 1.3.3.Threshold Voltage Roll-Off --
 1.3.4.Drain-Induced Barrier Lowering (DIBL) --
 1.3.5.Gate Leakage Current --
 1.3.5.1.Direct-Tunneling --
 1.3.5.2.Fowler-Nordheim Tunneling --
 1.3.5.3.Poole-Frenkel Emission and Trap-Assisted Tunneling --
 1.4.Features and Uniqueness of MOS Transistor --
 1.5.MOS in Deca-Nanometer --
 1.6.Technology Trends and Options --
 1.6.1.Technology Trends --
 1.6.2.Technology Options --
 1.6.2.1.Device Structures --
 1.6.2.2.Channel Engineering --
 1.6.2.3.Source and Drain Engineering --
 1.6.2.4.Gate Stack Engineering --
 1.6.3.More than Moore --
 1.7.Summary --
 References --
 2.High-k Dielectrics --
 2.1.High-k Candidates --
 2.2.Electronic Structure of Transition Metals and Rare Earth Metals --
 2.2.1.Electronegativity --
 2.2.2.Bond Radius --
 2.3.Material Properties of Elemental Transition Metal and Rare Metal Oxides --
 2.3.1.Atomic and Electronic Structures --
 2.3.2.Electronic Structure of Some High-k Oxides --
 2.3.2.1.Electronic Structure of Aluminum Oxide --
 2.3.2.2.Electronic Structure of Crystalline Hafnium Oxide --
 2.3.2.3.Electronic Structure of Crystalline Zirconium Oxide --
 2.3.2.4.Electronic Structure of Rare Earth Metal Oxides --
 2.4.Bandgap and Band Offset Energies --
 2.5.Bond Ionicity and Dielectric Constant --
 2.6.Carrier Effective Masses --
 2.7.Thermal Stability --
 2.7.1.Crystallization --
 2.7.2.Decomposition and Si Out-Diffusion --
 2.8.Disorders and Defects --
 2.8.1.Intrinsic Oxygen Vacancies --
 2.8.2.Oxygen Interstitials --
 2.8.3.Grain Boundary States --
 2.8.4.Extrinsic Defects --
 2.8.5.High-k/Si Interface Traps --
 2.9.Summary --
 References --
 3.Complex Forms of High-k Oxides --
 3.1.Introduction --
 3.2.Silicates and Aluminates Pseudo-Binary Alloys --
 3.3.Stoichiometric Binary Alloys --
 3.4.Doping --
 3.5.Thermal Stability and Phase Separation --
 3.6.Summary --
 References --
 4.Dielectric Interfaces --
 4.1.Introduction --
 4.2.High-k/Silicon Interface --
 4.2.1.Interfacial Bonding --
 4.2.2.Bond Strain, Relaxation, and Phase Diagrams --
 4.2.3.Band Offsets --
 4.3.High-k/Metal Interface --
 4.3.1.Need of Metal Gate --
 4.3.2.Band Offset Energies --
 4.3.3.Interface Stability --
 4.4.Summary --
 References --
 5.Impacts on Device Operation --
 5.1.Introduction --
 5.2.Gate Leakage Current --
 5.2.1.Current Conduction Mechanisms --
 5.2.2.Parameters Governing the Charge Transport --
 5.3.Threshold Voltage Control and Fermi-Level Pinning --
 5.4.Channel Mobility --
 5.5.Subthreshold Characteristics --
 5.6.Dielectric Breakdown --
 5.7.Hot-Carrier Effects --
 5.8.Temperature Instabilities --
 5.9.Summary --
 References --
 6.Fabrication Issues --
 6.1.Process Integration --
 6.2.Atomic Layer Deposition --
 6.3.Metal Organic Chemical Vapor Deposition --
 6.4.Physical Vapor Deposition --
 6.5.Etching --
 6.6.Summary --
 References --
 7.Conclusions.