VLSI for Artificial Intelligence and Neural Networks

Front Matter....Pages i-xiii
VLSI Design of a 3-D Highly Parallel Message-Passing Architecture....Pages 1-10
Architectural Design of the Rewrite Rule Machine Ensemble....Pages 11-22
A Dataflow Architecture for AI....Pages 23-32
Incremental Garbage Collection Scheme in KL1 and Its Architectural Support of PIM....Pages 33-45
COLIBRI: A Coprocessor for LISP based on RISC....Pages 47-56
A CAM Based Architecture for Production System Matching....Pages 57-66
SIMD Parallelism for Symbol Mapping....Pages 67-78
Logic Flow in Active Data....Pages 79-91
Parallel Analogue Computation for Real-Time Path Planning....Pages 93-99
An Extended Prolog Instruction Set for RISC Processors....Pages 101-108
A VLSI Engine for Structured Logic Programming....Pages 109-119
Performance Evaluation of a VLSI Associative Unifier in a WAM Based Environment....Pages 121-131
A Parallel Incremental Architecture for Prolog Program Execution....Pages 133-142
An Architectural Characterization of Prolog Execution....Pages 143-152
A Prolog Abstract Machine for Content-Addressable Memory....Pages 153-164
A Multi-Transputer Architecture for a Parallel Logic Machine....Pages 165-174
Computational Capabilities of Biologically-Realistic Analog Processing Elements....Pages 175-184
Analog VLSI Models of Mean Field Networks....Pages 185-194
An Analogue Neuron Suitable for a Data Frame Architecture....Pages 195-204
Fully Cascadable Analogue Synapses Using Distributed Feedback....Pages 205-213
Results from Pulse-Stream VLSI Neural Network Devices....Pages 215-224
Working Analogue Pulse-Firing Neural Network Chips....Pages 225-233
Pulse-Firing VLSI Neural Circuits for Fast Image Pattern Recognition....Pages 235-244
An Analog Circuit with Digital I/O for Synchronous Boltzmann Machines....Pages 245-254
The VLSI Implementation of the ∑ Architecture....Pages 255-263
A Cascadable VLSI Architecture for the Realization of Large Binary Associative Networks....Pages 265-274
Digital VLSI Implementations of an Associative Memory Based on Neural Networks....Pages 275-284
Probabilistic Bit Stream Neural Chip: Implementation....Pages 285-294
Binary Neural Network with Delayed Synapses....Pages 295-304
Syntactic Neural Networks in VLSI....Pages 305-314
A New Architectural Approach to Flexible Digital Neural Network Chip Systems....Pages 315-324
A VLSI Implementation of a Generic Systolic Synaptic Building Block for Neural Networks....Pages 325-334
A Learning Circuit That Operates by Discrete Means....Pages 335-343
A Compact and Fast Silicon Implementation for Layered Neural Nets....Pages 345-355
A Highly Parallel Digital Architecture for Neural Network Emulation....Pages 357-366
A Delay-Insensitive Neural Network Engine....Pages 367-376
A VLSI Implementation of Multi-Layered Neural Networks: 2-Performance....Pages 377-386
Efficient Implementation of Massive Neural Networks....Pages 387-397
Implementing Neural Networks with the Associative String Processor....Pages 399-408
Back Matter....Pages 409-412