SoC Physical Design: A Comprehensive Guide

Foreword
Foreword
Foreword
Preface
About the Book
Contents
About the Authors
Abbreviations
Introduction to Design of System on Chips and Future Trends in VLSI
	System on Chip (SoC)
	SoC Trends
	Components of SoC
		Analog Block
		Digital Cores
		Memory Blocks
		Macros
	Design Abstractions of SoC Design
		Abstractions
	Integration of SoC Design Components
	Trends in SoC Design Methodology
	SoC Design Styles
	Physical Design (PD) of SoC
		Fundamentals of Physical Design
			File Formats
			Process Design Kit (PDK)
			Physical Design Flow for Analog and Mixed Signal Designs
			Physical Design Tools
			Future of EDA Tools
		Future Trends of Systems
	References
SoC Physical Design Flow and Algorithms
	System on Chip (SoC) Physical Design
		SoC Core Design and Input-Output (IO) Design
	Physical Design Flow of SoC
		Floor Planning of SoC Design
			Cell Characterization and Wire Load Model
			Die Size Decision
			Power Plan and Power Strategy
			Floor Plan Verification
		Placement of SoC Design
			Pre Placement Stage
			Course Placement
			Placement Legalization
			High Fanout Net (HFN) Synthesis
			Placement Optimization
			Scan Chain Reordering
		Clock Tree Synthesis
		Global and Detailed Routing
	Physical Design Verification
		Design Rule Check (DRC)
		Layout vs. Schematic (LVS)
		Logical Equivalence Check (LEC)
	EDA Tools for Physical Design
Floor Plan and Placement of SoC Design
	Floor Planning of SoC Design
		Design Partitioning
		SoC Floor Plan
		SoC Power Plan
		Placement Considerations
	Two-Step Synthesis of SoC Design
	Placement of SoC Design
		Placement Methods
	Design Verification Checklist for Final Floor Plan
		Input for Floor Plan
	Floor Plan and Placement Validation
	EDA Tools in Physical Design
	Challenges in SOC Design Floor Plan and Placement
	References
Clock Tree Synthesis (CTS) in SoC Physical Design
	Digital Logic in SoC Design
	Sequential Cells in Digital Logic Design
	Pipelining
	Need for Clock Distribution
		Clock Parameters
	Clock Tree Synthesis
	Design Constraints
		Maximum Delay Constraint
		Minimum Delay Constraint
		Quality of Design
	CTS Topologies and PPA
	Types of Clock Trees
	Clock Tree Algorithms
	Design Challenges in the Clock Synthesis
Routing in SoC Physical Design
	Design Routing
	Major Challenges in Signal Routing
	Design Readiness for Signal Routing
	Signal Routing Steps
	Signal Routing Algorithms
		Maze Router or Lee Router Algorithm
	Routers in Physical Design Tools
	Design Signal Routing for Good Timing Performance
	Signal Routing for Signal Integrity in Designs
	Design Challenges in Signal Routing in SoC Designs
	References
System on Chip Design Finishing and Design for Manufacturability DFM
	Reliability and Design for Manufacturability (DFM) of SoC
		Signal Latch-Up in CMOS Standard Cells
			Guard Ring
			Well Tap Cells
			Creating Oxide Isolation Trenches
		Antenna Effect
		Cross Talk
			Cross Talk Timing Window Analysis
			Cross Talk Prevention Techniques
		IR Drop
		Electromigration (EM) Issue
		Fabrication Issues Leading to Signal Integrity and Reliability Issues
			Well Proximity Effect (WPE)
			Stress/Strain Effect
		Tap Cells
		Inserting Boundary Cap/End Cap Cells
		TiHi and TiLo Cells
		Decap Cells
		Spare Cells in Physical Design
	References
Physical Design Verification of SoC
	Physical Design Verification
	Static Timing Analysis (STA)
	Design Sign Off
	ECO for Design Fix
	EDA Tools for Sign Off
	Physical Design Verification by Formal Methods
		Model Checking
		Logic Equivalence Checking (LEC)
			Layout Versus Schematic (LVS)
		Electromigration
		IR and Cross Talk Analysis
	Gate Level Simulation
	Electrical Rule Check (ERC)
	Design Rule Check (DRC)
	Design Rule Violation (DRV) Checks
	Design Tape Out
	SoC Design Verification Challenges
	Available Solutions
	Machine Learning in Physical Design Verification
Advanced Packages and 3D-SoC Designs
	SoC Packaging
	Trends in Packaging
		Concept of Stacked Dies
		3D Integration Schemes
			2.5D-IC
			3D-IC
			Chiplets
		3D IC Constituents
		EDA Tools for 3D ICs
		Early Adopters of 3D-IC
	Future Trends of 3D IC Technology
	Reference
Current Trends of Semiconductor Systems and Physical Design
	Current Trends in Design Methodologies
		Optimal Logic Structure to Achieve PPA Goal
		Optimal Macro Placement
		Route Aware CTS, Pre-route to Post-route Correlation (Timing, Congestion)
	System-Level Technology Trends
	Future Trends of Systems [3]
	References
Question Bank
	Answers
Index