Next Generation Arithmetic: 4th International Conference, CoNGA 2023, Singapore, March 1-2, 2023, Proceedings

Preface
Organization
Contents
Lossless FFTs Using Posit Arithmetic
	1 Introduction
	2 Related Work
	3 Background
		3.1 Posits
		3.2 The Quire Register
		3.3 The FFT Algorithm
	4 Approach
		4.1 Accuracy
		4.2 Performance
	5 Results
		5.1 Accuracy
		5.2 Performance
	6 Conclusions and Future Work
	References
Bedot: Bit Efficient Dot Product for Deep Generative Models
	1 Introduction
	2 Background and Related Work
		2.1 Neural Networks and Emerging Architectures
		2.2 Quantization and Table Lookup
		2.3 Related Work
	3 Overview of Bedot
	4 Set Construction
		4.1 Detecting the Sensitive Layers
		4.2 Building Optimized Real Number Sets
		4.3 Fast Derivation of the Small Set from a Seed Set
		4.4 Enhancing Output Quality
		4.5 The Rounding Hint Table and Its Effect
	5 Set Mapping Based Inference
		5.1 Processing Element Utilizing Table Lookup
		5.2 Wired ROM Logic for Multiplication
		5.3 Combinational Logic Implementation of ROM
		5.4 SIMD MAC Unit Utilizing Our Lookup Units
		5.5 The Implementation of Rounding Hints
	6 Experiments
		6.1 Table Configurations and Accuracy
		6.2 Performance and Energy Estimation
	7 Conclusion
	References
A Paradigm for Interval-Aware Programming
	1 Introduction
	2 Relational Predicates
		2.1 IEEE 754 Floating-Point Numbers
		2.2 Posits
		2.3 Valids and Intervals
	3 Set-Valued Logic
		3.1 Set-Extended Relational Predicates
		3.2 Writing NaN-Aware Code
		3.3 Writing Interval-Aware Code
	4 Constraints
	5 Implementation
	6 Conclusion
	A Appendix
		A.1 The Dependency Problem
		A.2 Code Dependencies
		A.3 Piecewise Linear Interpolation
	References
Decoding-Free Two-Input Arithmetic for Low-Precision Real Numbers
	1 Introduction
	2 The Posit Format
	3 Standard Two-Input Arithmetic for Reals
	4 Mapping Method and Mathematical Formalization
		4.1 A Note on the Z Set
	5 Obtaining the Mapping: Problem Formulation and Its Solvability
	6 Application: Posit\"426830A 4,0\"526930B
		6.1 Quality Metrics
	7 Conclusions
	References
Hybrid SORN Hardware Accelerator for Support Vector Machines
	1 Introduction and Related Work
	2 Support Vector Machines
		2.1 Cascade SVM
	3 Hybrid SORN Arithmetic
		3.1 Conversions
	4 Hybrid SORN Support Vector Filtering
		4.1 FPGA Architecture
	5 Results
	6 Conclusion
	References
PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations
	1 Introduction
	2 Background and Related Work
		2.1 The IEEE-754 Standard
		2.2 Posit Format
	3 Posit Arithmetic Controller Design Methodology
		3.1 Posit Adder/Subtractor
		3.2 Posit Multiplier
		3.3 Control Unit
	4 Implementation Results and Evaluation
	5 Conclusion
	References
Fused Three-Input SORN Arithmetic
	1 Introduction and Related Work
	2 Type-II Unums and SORNs
		2.1 SORN Arithmetic
		2.2 Fused SORN Operations
	3 Fused Addition, Multiplication and Multiply-Add
		3.1 Accuracy
		3.2 FPGA Synthesis
		3.3 CMOS Synthesis
		3.4 Accuracy vs. Complexity
	4 Fused 2D and 3D Hypot Function
	5 Conclusion
	References
Towards a Better 16-Bit Number Representation for Training Neural Networks
	1 Introduction
	2 Related Work
	3 16-Bit Float and Posit Formats
		3.1 IEEE 754 Standard Type Float Formats
		3.2 DLFloat
		3.3 Posit
	4 Evaluation
	5 Results
	6 Hardware Implications
	7 Accuracy Analysis
		7.1 Accuracy Differences Between Posit16_1 and IEEE16_6
		7.2 Loss Behavior
		7.3 Effect on Weights
		7.4 Posit Accuracy in Training
	8 Shifting the Accuracy Peak
	9 Discussion and Conclusion
	References
Improving the Stability of Kalman Filters with Posit Arithmetic
	1 Introduction
	2 Introduction to Kalman Filters
		2.1 Classic Linear Kalman Filter
		2.2 Stability of Kalman Filters
	3 Precision of Computers
	4 Posit for Kalman Filters
		4.1 Estimating a Rotating Shaft
		4.2 Two Rotating Shaft with Relative Measurement
		4.3 INS/GPS Navigation
	5 Analysis on Performance
		5.1 Precision Metrics for Posit
		5.2 Analysis on Precision
		5.3 Analysis of Condition Number
	6 Conclusion
	7 Future Work
	References
Evaluation of the Use of Low Precision Floating-Point Arithmetic for Applications in Radio Astronomy
	1 Introduction
	2 Floating-Point Arithmetic
		2.1 Standard Floating-Point Formats
		2.2 Floating-Point Formats Supported by Major Hardware Manufactures
		2.3 Posits – An Emerging Number Format
	3 DSP Modules Used in Typical Radio Astronomy Applications
	4 Frequency Responses of the Channelizers, Tunable Filters and ReSamplers in SKA Mid CBF Implemented with float16, bfloat16, bfloat16+, posit16 and Similar Length Fixed-Point
		4.1 Frequency Responses of the Prototype-Filter for the 30 Channel VCC-OSPPFB Represented with float16, bfloat16, bfloat16+, posit16 and 19-Bit Fixed-Point
		4.2 Frequency Responses of the Prototype-Filter of the Imaging Channelizer Represented with float16, bfloat16, bfloat16+, posit16 and fixed19
		4.3 Frequency Responses of the Prototype-Filter of the Tunable Filter for Zoom Window Extraction Represented with float16, bfloat16, bfloat16 +, posit16 and fixed19
		4.4 Frequency Responses of the Fractional Delay Filter of the ReSampler Represented with float16, bfloat16, bfloat16+, posit16 and fixed19
	5 Conclusions and Future Work
	References
PLAUs: Posit Logarithmic Approximate Units to Implement Low-Cost Operations with Real Numbers
	1 Introduction
	2 Background
		2.1 Posit Arithmetic
		2.2 Related Work
	3 The Proposed Posit Logarithmic Approximate Units (PLAUs)
		3.1 Posit Multiplication
		3.2 Posit Division
		3.3 Posit Square Root
		3.4 Approximation Error
	4 Results and Analysis
		4.1 ASIC Synthesis Results
		4.2 Use Cases
	5 Conclusions
	References
Author Index