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دانلود کتاب Fundamentals of Digital Logic with Verilog Design

دانلود کتاب اصول منطق دیجیتال با طراحی Verilog

Fundamentals of Digital Logic with Verilog Design

مشخصات کتاب

Fundamentals of Digital Logic with Verilog Design

دسته بندی: برنامه نویسی: زبانهای مدل سازی
ویرایش: 3 
نویسندگان:   
سری:  
ISBN (شابک) : 0073380547, 9780073380544 
ناشر: McGraw-Hill Science/Engineering/Math 
سال نشر: 2013 
تعداد صفحات: 864 
زبان: English 
فرمت فایل : PDF (درصورت درخواست کاربر به PDF، EPUB یا AZW3 تبدیل می شود) 
حجم فایل: 6 مگابایت 

قیمت کتاب (تومان) : 49,000



کلمات کلیدی مربوط به کتاب اصول منطق دیجیتال با طراحی Verilog: کتابخانه، ادبیات کامپیوتر، زبان‌های توصیف سخت‌افزار (HDL)، Verilog



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توجه داشته باشید کتاب اصول منطق دیجیتال با طراحی Verilog نسخه زبان اصلی می باشد و کتاب ترجمه شده به فارسی نمی باشد. وبسایت اینترنشنال لایبرری ارائه دهنده کتاب های زبان اصلی می باشد و هیچ گونه کتاب ترجمه شده یا نوشته شده به فارسی را ارائه نمی دهد.


توضیحاتی در مورد کتاب اصول منطق دیجیتال با طراحی Verilog

مبانی منطق دیجیتال با طراحی Verilog برای یک دوره مقدماتی در طراحی منطق دیجیتال در نظر گرفته شده است. اهداف اصلی عبارتند از: (1) آموزش مفاهیم اساسی در طراحی دیجیتال دستی کلاسیک به دانش‌آموزان، و (2) به وضوح روش طراحی مدارهای دیجیتال امروزه با استفاده از ابزارهای CAD را نشان می‌دهد. استفاده از نرم‌افزار CAD به خوبی در کتاب ادغام شده است. برخی از ابزارهای عالی CAD به صورت رایگان در دسترس هستند. به عنوان مثال، Altera Corporation نرم افزار Quartus II CAD خود را دارد که برای پیاده سازی طرح ها در دستگاه های منطقی قابل برنامه ریزی مانند FPGA استفاده می شود.
نسخه وب نرم افزار Quartus II را می توان از وب سایت Alteras دانلود کرد و به صورت رایگان و بدون نیاز به استفاده از نیاز به اخذ مجوز ویرایش های قبلی این کتاب مجموعه ای از آموزش های استفاده از نرم افزار Quartus II در ضمیمه ها ارائه شده است. اکنون می توانید این آموزش ها را در وب سایت نویسنده ها بیابید. مجموعه دیگری از آموزش های مفید در مورد Quartus II را می توانید در وب سایت برنامه دانشگاه Alteras، که در www.altera.com/education/univ قرار دارد، بیابید.


توضیحاتی درمورد کتاب به خارجی

Fundamentals of Digital Logic With Verilog Design is intended for an introductory course in digital logic design. The main goals are (1) to teach students the fundamental concepts in classical manual digital design, and (2) illlustrate clearly the way in which digital circuits are designed today, using CAD tools.Use of CAD software is well integrated into the book. Some excellent CAD tools are available free of charge. For example, the Altera Corporation has its Quartus II CAD software, used for implementing designs in programmable logic devices such as FPGAs.
The Web Edition of the Quartus II software can be downloaded from Alteras website and used free of charge, without the need to obtain a license. Previous editions of this book a set of tutorials for using Quartus II software was provided in the appendices. These tutorials can now be found on the Authors website. Another set of useful tutorials about Quartus II can be found on Alteras University Program website, which is located at www.altera.com/education/univ



فهرست مطالب

Cover
Title
Copyright
Contents
Chapter 1 Introduction
	1.1 Digital Hardware
		1.1.1 Standard Chips
		1.1.2 Programmable Logic Devices
		1.1.3 Custom-Designed Chips
	1.2 The Design Process
	1.3 Structure of a Computer
	1.4 Logic Circuit Design in This Book
	1.5 Digital Representation of Information
		1.5.1 Binary Numbers
		1.5.2 Conversion between Decimal and Binary Systems
		1.5.3 ASCII Character Code
		1.5.4 Digital and Analog Information
	1.6 Theory and Practice
	Problems
	References
Chapter 2 Introduction to Logic Circuits
	2.1 Variables and Functions
	2.2 Inversion
	2.3 Truth Tables
	2.4 Logic Gates and Networks
		2.4.1 Analysis of a Logic Network
	2.5 Boolean Algebra
		2.5.1 The Venn Diagram
		2.5.2 Notation and Terminology
		2.5.3 Precedence of Operations
	2.6 Synthesis Using AND, OR, and NOT Gates
		2.6.1 Sum-of-Products and Product-of-Sums Forms
	2.7 NAND and NOR Logic Networks
	2.8 Design Examples
		2.8.1 Three-Way Light Control
		2.8.2 Multiplexer Circuit
		2.8.3 Number Display
	2.9 Introduction to CAD Tools
		2.9.1 Design Entry
		2.9.2 Logic Synthesis
		2.9.3 Functional Simulation
		2.9.4 Physical Design
		2.9.5 Timing Simulation
		2.9.6 Circuit Implementation
		2.9.7 Complete Design Flow
	2.10 Introduction to Verilog
		2.10.1 Structural Specification of Logic Circuits
		2.10.2 Behavioral Specification of Logic Circuits
		2.10.3 Hierarchical Verilog Code
		2.10.4 How NOT to Write Verilog Code
	2.11 Minimization and Karnaugh Maps
	2.12 Strategy for Minimization
		2.12.1 Terminology
		2.12.2 Minimization Procedure
	2.13 Minimization of Product-of-Sums Forms
	2.14 Incompletely Specified Functions
	2.15 Multiple-Output Circuits
	2.16 Concluding Remarks
	2.17 Examples of Solved Problems
	Problems
	References
Chapter 3 Number Representation and Arithmetic Circuits
	3.1 Positional Number Representation
		3.1.1 Unsigned Integers
		3.1.2 Octal and Hexadecimal Representations
	3.2 Addition of Unsigned Numbers
		3.2.1 Decomposed Full-Adder
		3.2.2 Ripple-Carry Adder
		3.2.3 Design Example
	3.3 Signed Numbers
		3.3.1 Negative Numbers
		3.3.2 Addition and Subtraction
		3.3.3 Adder and Subtractor Unit
		3.3.4 Radix-Complement Schemes*
		3.3.5 Arithmetic Overflow
		3.3.6 Performance Issues
	3.4 Fast Adders
		3.4.1 Carry-Lookahead Adder
	3.5 Design of Arithmetic Circuits Using CAD Tools
		3.5.1 Design of Arithmetic Circuits Using Schematic Capture
		3.5.2 Design of Arithmetic Circuits Using Verilog
		3.5.3 Using Vectored Signals
		3.5.4 Using a Generic Specification
		3.5.5 Nets and Variables in Verilog
		3.5.6 Arithmetic Assignment Statements
		3.5.7 Module Hierarchy in Verilog Code
		3.5.8 Representation of Numbers in Verilog Code
	3.6 Multiplication
		3.6.1 Array Multiplier for Unsigned Numbers
		3.6.2 Multiplication of Signed Numbers
	3.7 Other Number Representations
		3.7.1 Fixed-Point Numbers
		3.7.2 Floating-Point Numbers
		3.7.3 Binary-Coded-Decimal Representation
	3.8 Examples of Solved Problems
	Problems
	References
Chapter 4 Combinational-Circuit Building Blocks
	4.1 Multiplexers
		4.1.1 Synthesis of Logic Functions Using Multiplexers
		4.1.2 Multiplexer Synthesis Using Shannon\'s Expansion
	4.2 Decoders
		4.2.1 Demultiplexers
	4.3 Encoders
		4.3.1 Binary Encoders
		4.3.2 Priority Encoders
	4.4 Code Converters
	4.5 Arithmetic Comparison Circuits
	4.6 Verilog for Combinational Circuits
		4.6.1 The Conditional Operator
		4.6.2 The If-Else Statement
		4.6.3 The Case Statement
		4.6.4 The For Loop
		4.6.5 Verilog Operators
		4.6.6 The Generate Construct
		4.6.7 Tasks and Functions
	4.7 Concluding Remarks
	4.8 Examples of Solved Problems
	Problems
	References
Chapter 5 Flip-Flops, Registers, and Counters
	5.1 Basic Latch
	5.2 Gated SR Latch
		5.2.1 Gated SR Latch with NAND Gates
	5.3 Gated D Latch
		5.3.1 Effects of Propagation Delays
	5.4 Edge-Triggered D Flip-Flops
		5.4.1 Master-Slave D Flip-Flop
		5.4.2 Other Types of Edge-Triggered D Flip-Flops
		5.4.3 D Flip-Flops with Clear and Preset
		5.4.4 Flip-Flop Timing Parameters
	5.5 T Flip-Flop
	5.6 JK Flip-Flop
	5.7 Summary of Terminology
	5.8 Registers
		5.8.1 Shift Register
		5.8.2 Parallel-Access Shift Register
	5.9 Counters
		5.9.1 Asynchronous Counters
		5.9.2 Synchronous Counters
		5.9.3 Counters with Parallel Load
	5.10 Reset Synchronization
	5.11 Other Types of Counters
		5.11.1 BCD Counter
		5.11.2 Ring Counter
		5.11.3 Johnson Counter
		5.11.4 Remarks on Counter Design
	5.12 Using Storage Elements with CAD Tools
		5.12.1 Including Storage Elements in Schematics
		5.12.2 Using Verilog Constructs for Storage Elements
		5.12.3 Blocking and Non-Blocking Assignments
		5.12.4 Non-Blocking Assignments for Combinational Circuits
		5.12.5 Flip-Flops with Clear Capability
	5.13 Using Verilog Constructs for Registers and Counters
		5.13.1 Flip-Flops and Registers with Enable Inputs
		5.13.2 Shift Registers with Enable Inputs
	5.14 Design Example
		5.14.1 Reaction Timer
		5.14.2 Register Transfer Level (RTL) Code
	5.15 Timing Analysis of Flip-flop Circuits
		5.15.1 Timing Analysis with Clock Skew
	5.16 Concluding Remarks
	5.17 Examples of Solved Problems
	Problems
	References
Chapter 6 Synchronous Sequential Circuits
	6.1 Basic Design Steps
		6.1.1 State Diagram
		6.1.2 State Table
		6.1.3 State Assignment
		6.1.4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions
		6.1.5 Timing Diagram
		6.1.6 Summary of Design Steps
	6.2 State-Assignment Problem
		6.2.1 One-Hot Encoding
	6.3 Mealy State Model
	6.4 Design of Finite State Machines Using CAD Tools
		6.4.1 Verilog Code for Moore-Type FSMs
		6.4.2 Synthesis of Verilog Code
		6.4.3 Simulating and Testing the Circuit
		6.4.4 Alternative Styles of Verilog Code
		6.4.5 Summary of Design Steps When Using CAD Tools
		6.4.6 Specifying the State Assignment in Verilog Code
		6.4.7 Specification of Mealy FSMs Using Verilog
	6.5 Serial Adder Example
		6.5.1 Mealy-Type FSM for Serial Adder
		6.5.2 Moore-Type FSM for Serial Adder
		6.5.3 Verilog Code for the Serial Adder
	6.6 State Minimization
		6.6.1 Partitioning Minimization Procedure
		6.6.2 Incompletely Specified FSMs
	6.7 Design of a Counter Using the Sequential Circuit Approach
		6.7.1 State Diagram and State Table for a Modulo-8 Counter
		6.7.2 State Assignment
		6.7.3 Implementation Using D-Type Flip-Flops
		6.7.4 Implementation Using JK-Type Flip-Flops
		6.7.5 Example—A Different Counter
	6.8 FSM as an Arbiter Circuit
	6.9 Analysis of Synchronous Sequential Circuits
	6.10 Algorithmic State Machine (ASM) Charts
	6.11 Formal Model for Sequential Circuits
	6.12 Concluding Remarks
	6.13 Examples of Solved Problems
	Problems
	References
Chapter 7 Digital System Design
	7.1 Bus Structure
		7.1.1 Using Tri-State Drivers to Implement a Bus
		7.1.2 Using Multiplexers to Implement a Bus
		7.1.3 Verilog Code for Specification of Bus Structures
	7.2 Simple Processor
	7.3 A Bit-Counting Circuit
	7.4 Shift-and-Add Multiplier
	7.5 Divider
	7.6 Arithmetic Mean
	7.7 Sort Operation
	7.8 Clock Synchronization and Timing Issues
		7.8.1 Clock Distribution
		7.8.2 Flip-Flop Timing Parameters
		7.8.3 Asynchronous Inputs to Flip-Flops
		7.8.4 Switch Debouncing
	7.9 Concluding Remarks
	Problems
	References
Chapter 8 Optimized Implementation of Logic Functions
	8.1 Multilevel Synthesis
		8.1.1 Factoring
		8.1.2 Functional Decomposition
		8.1.3 Multilevel NAND and NOR Circuits
	8.2 Analysis of Multilevel Circuits
	8.3 Alternative Representations of Logic Functions
		8.3.1 Cubical Representation
		8.3.2 Binary Decision Diagrams
	8.4 Optimization Techniques Based on Cubical Representation
		8.4.1 A Tabular Method for Minimization
		8.4.2 A Cubical Technique for Minimization
		8.4.3 Practical Considerations
	8.5 Concluding Remarks
	8.6 Examples of Solved Problems
	Problems
	References
Chapter 9 Asynchronous Sequential Circuits
	9.1 Asynchronous Behavior
	9.2 Analysis of Asynchronous Circuits
	9.3 Synthesis of Asynchronous Circuits
	9.4 State Reduction
	9.5 State Assignment
		9.5.1 Transition Diagram
		9.5.2 Exploiting Unspecified Next-State Entries
		9.5.3 State Assignment Using Additional State Variables
		9.5.4 One-Hot State Assignment
	9.6 Hazards
		9.6.1 Static Hazards
		9.6.2 Dynamic Hazards
		9.6.3 Significance of Hazards
	9.7 A Complete Design Example
		9.7.1 The Vending-Machine Controller
	9.8 Concluding Remarks
	9.9 Examples of Solved Problems
	Problems
	References
Chapter 10 Computer Aided Design Tools
	10.1 Synthesis
		10.1.1 Netlist Generation
		10.1.2 Gate Optimization
		10.1.3 Technology Mapping
	10.2 Physical Design
		10.2.1 Placement
		10.2.2 Routing
		10.2.3 Static Timing Analysis
	10.3 Concluding Remarks
	References
Chapter 11 Testing of Logic Circuits
	11.1 Fault Model
		11.1.1 Stuck-at Model
		11.1.2 Single and Multiple Faults
		11.1.3 CMOS Circuits
	11.2 Complexity of a Test Set
	11.3 Path Sensitizing
		11.3.1 Detection of a Specific Fault
	11.4 Circuits with Tree Structure
	11.5 Random Tests
	11.6 Testing of Sequential Circuits
		11.6.1 Design for Testability
	11.7 Built-in Self-Test
		11.7.1 Built-in Logic Block Observer
		11.7.2 Signature Analysis
		11.7.3 Boundary Scan
	11.8 Printed Circuit Boards
		11.8.1 Testing of PCBs
		11.8.2 Instrumentation
	11.9 Concluding Remarks
	Problems
	References
Appendix A: Verilog Reference
	A.1 Documentation in Verilog Code
	A.2 White Space
	A.3 Signals in Verilog Code
	A.4 Identifier Names
	A.5 Signal Values, Numbers, and Parameters
		A.5.1 Parameters
	A.6 Net and Variable Types
		A.6.1 Nets
		A.6.2 Variables
		A.6.3 Memories
	A.7 Operators
	A.8 Verilog Module
	A.9 Gate Instantiations
	A.10 Concurrent Statements
		A.10.1 Continuous Assignments
		A.10.2 Using Parameters
	A.11 Procedural Statements
		A.11.1 Always and Initial Blocks
		A.11.2 The If-Else Statement
		A.11.3 Statement Ordering
		A.11.4 The Case Statement
		A.11.5 Casez and Casex Statements
		A.11.6 Loop Statements
		A.11.7 Blocking versus Non-blocking Assignments for Combinational Circuits
	A.12 Using Subcircuits
		A.12.1 Subcircuit Parameters
		A.12.2 The Generate Capability
	A.13 Functions and Tasks
	A.14 Sequential Circuits
		A.14.1 A Gated D Latch
		A.14.2 D Flip-Flop
		A.14.3 Flip-Flops with Reset
		A.14.4 Registers
		A.14.5 Shift Registers
		A.14.6 Counters
		A.14.7 An Example of a Sequential Circuit
		A.14.8 Moore-Type Finite State Machines
		A.14.9 Mealy-Type Finite State Machines
	A.15 Guidelines for Writing Verilog Code
	A.16 Concluding Remarks
	References
Appendix B: Implementation Technology
	B.1 Transistor Switches
	B.2 NMOS Logic Gates
	B.3 CMOS Logic Gates
		B.3.1 Speed of Logic Gate Circuits
	B.4 Negative Logic System
	B.5 Standard Chips
		B.5.1 7400-Series Standard Chips
	B.6 Programmable Logic Devices
		B.6.1 Programmable Logic Array (PLA)
		B.6.2 Programmable Array Logic (PAL)
		B.6.3 Programming of PLAs and PALs
		B.6.4 Complex Programmable Logic Devices (CPLDs)
		B.6.5 Field-Programmable Gate Arrays
	B.7 Custom Chips, Standard Cells, and Gate Arrays
	B.8 Practical Aspects
		B.8.1 MOSFET Fabrication and Behavior
		B.8.2 MOSFET On-Resistance
		B.8.3 Voltage Levels in Logic Gates
		B.8.4 Noise Margin
		B.8.5 Dynamic Operation of Logic Gates
		B.8.6 Power Dissipation in Logic Gates
		B.8.7 Passing 1s and 0s Through Transistor Switches
		B.8.8 Transmission Gates
		B.8.9 Fan-in and Fan-out in Logic Gates
		B.8.10 Tri-state Drivers
	B.9 Static Random Access Memory (SRAM)
		B.9.1 SRAM Blocks in PLDs
	B.10 Implementation Details for SPLDs, CPLDs, and FPGAs
		B.10.1 Implementation in FPGAs
	B.11 Concluding Remarks
	B.12 Examples of Solved Problems
	Problems
	References
Answers
Index
	A
	B
	C
	D
	E
	F
	G
	H
	I
	J
	K
	L
	M
	N
	O
	P
	Q
	R
	S
	T
	U
	W
	X
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