Fundamentals of Digital Electronics (Lecture Notes in Electrical Engineering, 623)

Preface
Acknowledgements
Contents
About the Author
1 Overview of Digital Signal Processing
	1.1 Types of Signals
		1.1.1 Analog Signal
		1.1.2 Digital Signal
	1.2 Basic Characteristics of Digital Signal
		1.2.1 Rise and Fall Times
		1.2.2 Period, Frequency and Duty Cycle
		1.2.3 Signal Processing
	1.3 Analog Signal Processing
	1.4 Digital Signal Processing
		1.4.1 Advantages
		1.4.2 Digital SMPS
		1.4.3 Digital Hardware
	1.5 Simplifying Logic Functions
		1.5.1 Basic Logical Operators
		1.5.2 Boolean Algebra
		1.5.3 De Morgan Laws
		1.5.4 Shannon Theorems
		1.5.5 Simplification of Logic Functions
	1.6 Hardware Description Language
	References
2 Logic Gates
	2.1 Introduction
	2.2 Basic Logic Gates
		2.2.1 OR Gate
		2.2.2 AND Gate
		2.2.3 NOT Gate (Inverter)
		2.2.4 Active High and Active Low Input Signals
	2.3 Universal Logic Gates
		2.3.1 NOR Gate
		2.3.2 NAND Gate
	2.4 General Purpose Logic Gates
		2.4.1 AND-OR-INVERT Gate
		2.4.2 Expandable AND-OR-INVERT Gate
		2.4.3 XOR Gate
		2.4.4 XNOR Gate
3 Combinational Logic Minimization
	3.1 Overview of Combinational Logic Design
		3.1.1 General Design Approach
	3.2 Logic Function in SOP Form
		3.2.1 Minterm
		3.2.2 Obtaining Logic Function
	3.3 Logic Function in POS Form
		3.3.1 Maxterm
		3.3.2 Obtaining Logic Function
	3.4 Algebraic Method for Logic Simplification
		3.4.1 Simplifying Logic Function in SOP Form
		3.4.2 Simplifying Logic Function in POS Form
		3.4.3 Transformation Between SOP and POS Forms
	3.5 Karnaugh Mapping
		3.5.1 K-map with Two Variables
		3.5.2 K-map with Three Variables
		3.5.3 K-map with Four Variables
		3.5.4 Variable-Entered K-map
		3.5.5 Don’t-Care Conditions
		3.5.6 Logic Function in POS Form
	3.6 Quine-McCluskey Method
		3.6.1 Definition of Terms
		3.6.2 Illustration
	3.7 Hazards
		3.7.1 Causes
		3.7.2 Types of Hazards
		3.7.3 Avoiding Hazards
	References
4 Combinational Logic Devices
	4.1 Introduction
	4.2 Multiplexers
		4.2.1 Operation
		4.2.2 Implementing 3-Variable Truth Table Using 8:1 MUX
		4.2.3 Implementing 4-Variable Truth Table Using 8:1 MUX
		4.2.4 Direct Implementation of Logic Function
		4.2.5 Cascading Multiplexers
	4.3 Demultiplexers
		4.3.1 Operation
		4.3.2 Cascading Demultiplexers
	4.4 Decoders
		4.4.1 Operation
		4.4.2 Demultiplexers as Decoders
		4.4.3 Applications of Decoders
		4.4.4 Implementing Logic Functions
		4.4.5 BCD to Decimal Decoder/Driver
		4.4.6 BCD to 7-Segment Decoder/Driver
	4.5 Encoders
		4.5.1 Decimal-to-BCD Encoder
		4.5.2 Priority Encoders
	4.6 Magnitude Comparators
		4.6.1 Operation
		4.6.2 Logic Function for 1-Bit Comparator
		4.6.3 Logic Function for 2-Bit Comparator
		4.6.4 Cascading Magnitude Comparators
	Reference
5 Number Systems and Binary Codes
	5.1 Types of Number Systems
	5.2 Decimal Number System
	5.3 Binary Number System
		5.3.1 Decimal-Binary Conversion
		5.3.2 Binary-Decimal Conversion
		5.3.3 Binary Coded Decimal
		5.3.4 Excess-3 Code
	5.4 Octal Number System
		5.4.1 Octal-Binary Conversion
		5.4.2 Binary-Octal Conversion
		5.4.3 Octal-Decimal Conversion
		5.4.4 Decimal-Octal Conversion
	5.5 Hexadecimal Number System
		5.5.1 Hexadecimal-Binary Conversion
		5.5.2 Binary-Hexadecimal Conversion
		5.5.3 Hexadecimal-Decimal Conversion
		5.5.4 Decimal-Hexadecimal Conversion
		5.5.5 Hexadecimal-Octal Conversion
		5.5.6 Octal-Hexadecimal Conversion
	5.6 Binary Codes
		5.6.1 Unipolar Straight Binary
		5.6.2 Unipolar Gray Code
		5.6.3 Bipolar Offset Binary
		5.6.4 Bipolar Binary Two’s Complement
	5.7 Alphanumeric Codes
		5.7.1 ASCII and EBCDIC Schemes
		5.7.2 Unicode Standard
	5.8 Bit Error Detection
		5.8.1 Types of Random Bit Errors
		5.8.2 Error Detection Methods
		5.8.3 Single Bit Parity Check
		5.8.4 Two Dimensional Parity Check
		5.8.5 Checksum
		5.8.6 Cyclic Redundancy Check
	References
6 Arithmetic Operations and Circuits
	6.1 Binary Arithmetic Operations
	6.2 Binary Addition
		6.2.1 Addition of 4-Bit Binary Numbers
		6.2.2 Half Adder
		6.2.3 Full Adder
		6.2.4 Parallel Adder
		6.2.5 Fast Adder
		6.2.6 Cascading Fast Adders
	6.3 Binary Subtraction
		6.3.1 Rules for Binary Subtraction
		6.3.2 Coding Methods
		6.3.3 Signed Magnitude
		6.3.4 One’s Complement
		6.3.5 Two’s Complement
	6.4 Arithmetic Operations with Two’s Complement Codes
		6.4.1 Illustrations
		6.4.2 Parallel Adder for Addition and Subtraction
		6.4.3 Overflow Detection and Correction
	6.5 Binary Multiplication and Division
		6.5.1 Multiplication
		6.5.2 Division
	References
7 Clock and Timing Signals
	7.1 Introduction
		7.1.1 Clock Signal Network
	7.2 Quality Requirements of Clock Signals
		7.2.1 Clock Jitter
	7.3 Generating Clock and Timing Signals
		7.3.1 Reference Crystal Oscillator
		7.3.2 Clock Generator Using Standard Gates
	7.4 Schmitt Trigger
		7.4.1 Operation
		7.4.2 Hysteresis
	7.5 Timer IC, 555
		7.5.1 Astable Operation
		7.5.2 Monostable Operation
	7.6 Monostable Multivibrators
		7.6.1 Non-retriggerable Monostable Multivibrator
		7.6.2 Retriggerable Monostable Multivibrator
	References
8 Latches and Flip-Flops
	8.1 Introduction
	8.2 Latches
		8.2.1 SR Latch with NOR Gates
		8.2.2 S′R′ Latch with NAND Gates
		8.2.3 SR Latch for Eliminating Contact Bounce Errors
		8.2.4 Gated SR Latch
		8.2.5 D Latch
	8.3 Flip-Flops
		8.3.1 Function Table
		8.3.2 Applications
		8.3.3 D Flip-Flop
		8.3.4 T Flip-Flop
		8.3.5 JK Flip-Flop
	8.4 Flip-Flop Timing Requirements
		8.4.1 Set-up and Hold Time
	8.5 Flip-Flops Using Master-Slave Latches
		8.5.1 D Master-Slave Flip-Flop
	8.6 State Transition Diagram of Flip-Flop
	References
9 Registers
	9.1 Introduction
	9.2 Storage Registers
		9.2.1 Simple Storage Register
		9.2.2 Standard Storage Register
	9.3 Basic Shift Registers
		9.3.1 Serial-In/Parallel-Out Shift Register
		9.3.2 Parallel-In/Serial-Out Shift Register
		9.3.3 Serial-In/Serial-Out Shift Register
		9.3.4 Parallel-In/Parallel-Out Shift Register
	9.4 Applications of Shift Registers
		9.4.1 Ring Counter
		9.4.2 Johnson Counter
		9.4.3 Linear Feedback Shift Register
		9.4.4 Serial Adder
	9.5 Universal Shift Register
		9.5.1 Mode Select Function
	Reference
10 Counters
	10.1 Introduction
		10.1.1 Understanding Counters
	10.2 Asynchronous Counters
		10.2.1 Binary Ripple Counter
		10.2.2 BCD Ripple Counter
	10.3 Synchronous Counters
		10.3.1 Binary Counter
		10.3.2 BCD Counter
		10.3.3 Up-Down Counters
	10.4 Decoding Counter States and Glitches
		10.4.1 Decoder for Synchronous Counters
		10.4.2 Decoder for Asynchronous Counters
	10.5 Cascading Counters
		10.5.1 Terminal Count for Cascading
		10.5.2 Cascading Standard IC Counters
	10.6 Digital Clock
		10.6.1 Operation
	10.7 Design of Counters
		10.7.1 Mod-6 Binary Counter
		10.7.2 Mod-6 Gray Code Counter
	Reference
11 Signal Converter Architectures
	11.1 Overview of Signal Conversion
		11.1.1 Pre-processing and Post-processing
		11.1.2 ADC
		11.1.3 DAC
		11.1.4 Standard ICs for ADCs and DACs
	11.2 Analog Components for Signal Conversion
		11.2.1 Sample-Hold Amplifier
		11.2.2 Anti-aliasing Filter
		11.2.3 Reconstruction Filter
		11.2.4 Operational Amplifier
	11.3 ADC Architectures
		11.3.1 Flash ADC
		11.3.2 Successive Approximation ADC
		11.3.3 Dual Slope ADC
		11.3.4 Sigma-Delta ADC
	11.4 DAC Architectures
		11.4.1 Binary-Weighted Input DAC
		11.4.2 R-2R Ladder DAC
	References
12 Programmable Logic Devices
	12.1 Introduction
	12.2 Logic Devices Programmed by Manufacturers
		12.2.1 ROM
		12.2.2 Mask ROM
		12.2.3 Applications of ROM
	12.3 Simple Programmable Logic Devices
		12.3.1 Programmable Read-Only Memory
		12.3.2 Programmable Logic Array
		12.3.3 Programmable Array Logic
		12.3.4 Generic Array Logic
	12.4 Complex Programmable Logic Device
		12.4.1 Basic Architecture
	12.5 Field Programmable Gate Array
		12.5.1 General Architecture
	References
13 Design of Sequential Logic Circuits
	13.1 FSM Models
		13.1.1 General Models of Moore and Mealy Machines
		13.1.2 Designing Sequential Logic Circuits
	13.2 Sequence Detector Using Moore Machine
		13.2.1 State Transition Diagram
		13.2.2 Next State Table
		13.2.3 Number of Flip-Flops
		13.2.4 Encoding of States
		13.2.5 Final State Table with Binary Encoding
		13.2.6 Logic Functions with Binary Encoding
		13.2.7 Sequential Logic Circuit with Binary Encoding
		13.2.8 Sequential Logic Circuit with Gray Code Encoding
	13.3 Sequence Detector Using Mealy Machine
		13.3.1 State Transition Diagram
		13.3.2 Next State Table
		13.3.3 Sequential Logic Circuit with Binary Encoding
		13.3.4 Sequential Logic Circuit with Gray Code Encoding
	13.4 Algorithmic State Machine Chart
	13.5 State Reduction
		13.5.1 Row Elimination Method
		13.5.2 Implication Table Method
	References
14 Technologies and General Parameters of ICs
	14.1 Logic Families
		14.1.1 TTL Technology
		14.1.2 CMOS Technology
		14.1.3 BiCMOS Technology
	14.2 Generic Application Requirements
		14.2.1 Logic Switching Voltage Levels
		14.2.2 Noise Margin
		14.2.3 Fan-Out
		14.2.4 Absolute Maximum Ratings
		14.2.5 ESD Requirements for CMOS Devices
	14.3 Logic Pulser and Probe
	References
Appendix  Erasable PROMs
A.1 Erasable PROMs
A.2 Structure of Memory Cell
A.3 Logic Levels
A.3.1 Electrically Programming Floating Gate Memory Cells
A.3.2 Erasing Operation
A.4 UVEPROM
A.5 EEPROM
A.6 Flash Memory
Index