Digital Design of Signal Processing Systems: A Practical Approach

DIGITAL DESIGN OF SIGNAL PROCESSING SYSTEMS: A PRACTICAL APPROACH......Page 1
Contents......Page 7
Preface......Page 17
Acknowledgments......Page 21
1.1 Introduction......Page 23
1.3.1 Principles......Page 25
1.3.2 Multi-core Systems......Page 28
1.3.3 NoC-based MPSoC......Page 29
1.4.1 Digital Receiver for a Voice Communication System......Page 30
1.5.1 Design......Page 32
1.7 Synchronous Digital Hardware Systems......Page 33
1.8 Design Strategies......Page 34
1.8.1 Example of Design Partitioning......Page 36
1.8.2 NoC-based SoC for Carrier-class VoIP Media Gateway......Page 38
1.8.3 Design Flow Migration......Page 40
References......Page 41
2.1 Overview......Page 43
2.2.2 What is Verilog?......Page 44
2.4 Logic Synthesis......Page 45
2.5.1 Modules......Page 46
2.5.2 Design Partitioning......Page 47
2.5.3 Hierarchical Design......Page 48
2.5.4 Logic Values......Page 51
2.5.6 Variable Declaration......Page 52
2.6 Four Levels of Abstraction......Page 53
2.6.2 Gate Level or Structural Modeling......Page 54
2.6.3 Dataflow Level......Page 55
2.6.4 Behavioral Level......Page 61
2.6.5 Verilog Tasks......Page 77
2.6.7 Signed Arithmetic......Page 78
2.7.1 Introduction to Verification......Page 79
2.7.2 Approaches to Testing a Digital Design......Page 80
2.7.4 Methods for Generating Test Cases......Page 81
2.7.5 Transaction-level Modeling......Page 82
2.9.1 Data Types......Page 83
2.9.2 Module Instantiation and Port Listing......Page 85
2.9.3 Constructs of the C/C++ Type......Page 86
2.9.5 The always Procedural Block......Page 87
2.9.7 The unique and priority Case Statements......Page 88
2.9.9 Functions and Tasks......Page 89
2.9.10 The Interface......Page 90
2.9.11 Classes......Page 92
2.9.12 Direct Programming Interface (DPI)......Page 94
2.9.13 Assertion......Page 95
2.9.15 Randomization......Page 96
Exercises......Page 97
References......Page 102
3.1 Overview......Page 103
3.2.1 Principles......Page 105
3.2.2 Example: Requirements and Specifications of a UHF Software-defined Radio......Page 107
3.2.3 Coding Guidelines for High-level Behavioral Description......Page 108
3.2.4 Fixed-point versus Floating-point Hardware......Page 110
3.3.2 Two’s Complement Representation......Page 111
3.3.3 Computing Two’s Complement of a Signed Number......Page 112
3.3.4 Scaling......Page 113
3.4 Floating-point Format......Page 114
3.4.1 Normalized and Denormalized Values......Page 115
3.4.2 Floating-point Arithmetic Addition......Page 117
3.5.1 Introducing Qn.m......Page 118
3.5.2 Floating-point to Fixed-point Conversion of Numbers......Page 119
3.5.4 Multiplication in Q Format......Page 120
3.5.5 Bit Growth in Fixed-point Arithmetic......Page 123
3.5.6 Overflow and Saturation......Page 124
3.5.7 Two’s Complement Intermediate Overflow Property......Page 125
3.5.8 Corner Cases......Page 127
3.5.9 Code Conversion and Checking the Corner Case......Page 128
3.5.10 Rounding the Product in Fixed-point Multiplication......Page 129
3.5.11 MATLAB®  Support for Fixed-point Arithmetic......Page 132
3.5.12 SystemC Support for Fixed-point Arithmetic......Page 133
3.6 Floating-point to Fixed-point Conversion......Page 134
3.7 Block Floating-point Format......Page 135
3.8.1 Infinite Impulse Response Filter......Page 137
3.8.2 Quantization of IIR Filter Coefficients......Page 139
3.8.3 Coefficient Quantization Analysis of a Second-order Section......Page 145
3.8.4 Folded FIR Filters......Page 148
3.8.5 Coefficient Quantization of an FIR Filter......Page 149
Exercises......Page 150
References......Page 154
4.1 Introduction......Page 155
4.2 Discrete Real-time Systems......Page 156
4.3 Synchronous Digital Hardware Systems......Page 158
4.4.1 Introduction to KPN......Page 159
4.4.2 KPN for Modeling Streaming Applications......Page 161
4.4.4 Modified KPN and MPSoC......Page 166
4.4.5 Case Study: GMSK Communication Transmitter......Page 167
4.5.1 Introduction......Page 170
4.5.2 Block Diagram......Page 171
4.5.4 Dataflow Graph or Data Dependency Graph......Page 173
4.5.6 Single-rate and Multi-rate SDFGs......Page 178
4.5.8 Cyclo-static DFG......Page 180
4.5.10 Control Flow Graphs......Page 182
4.5.11 Finite State Machine......Page 183
4.6.1 Iteration Period......Page 184
4.6.3 Latency......Page 185
4.7.1 The Design Space......Page 186
4.7.2 Pipelining......Page 187
4.7.3 Selecting Basic Building Blocks......Page 189
4.8 DFG to HW Synthesis......Page 190
4.8.1 Mapping a Multi-rate DFG in Hardware......Page 191
4.8.2 Centralized Controller for DFG Realization......Page 193
Exercises......Page 195
References......Page 203
5.2 Embedded Processors and Arithmetic Units in FPGAs......Page 205
5.3 Instantiation of Embedded Blocks......Page 208
5.3.1 Example of Optimized Mapping......Page 212
5.3.2 Design Optimization for the Target Technology......Page 214
5.5.1 Overview......Page 216
5.5.2 Half Adders and Full Adders......Page 217
5.5.3 Ripple Carry Adder......Page 218
5.5.5 Carry Look-ahead Adder......Page 220
5.5.7 Binary Carry Look-ahead Adder......Page 225
5.5.9 Conditional Sum Adder......Page 231
5.5.10 Carry Select Adder......Page 237
5.6 Barrel Shifter......Page 239
5.7.3 Dot Notation......Page 243
5.8.1 Introduction......Page 244
5.8.2 Partial Product Generation......Page 245
5.8.3 Partial Product Reduction......Page 246
5.8.4 A Decomposed Multiplier......Page 252
5.8.5 Optimized Compressors......Page 253
5.8.6 Single- and Multiple-column Counters......Page 254
5.9.1 Basics......Page 256
5.9.2 Sign Extension Elimination......Page 257
5.9.3 String Property......Page 259
5.9.4 Modified Booth Recoding Multiplier......Page 260
5.9.5 Modified Booth Recoded Multiplier in RTL Verilog......Page 262
5.11 Algorithm Transformations for CSA......Page 265
Exercises......Page 269
References......Page 273
6.1 Introduction......Page 275
6.2 Canonic Signed Digit Representation......Page 276
6.4 Multiplication by a Constant in a Signal Processing Algorithm......Page 277
6.5 Optimized DFG Transformation......Page 278
6.6.1 Introduction......Page 283
6.6.2 Example: Five-coefficient Filter......Page 284
6.6.3 Transposed Direct-form FIR Filter......Page 291
6.6.4 Example: TDF Architecture......Page 294
6.6.5 Hybrid FIR Filter Structure......Page 298
6.7.1 Sub-graph Sharing......Page 299
6.7.2 Common Sub-expression Elimination......Page 301
6.8.1 Basics......Page 305
6.8.2 Example: FIR Filter Design......Page 309
6.8.3 M-parallel Sub-filter-based Design......Page 313
6.9 FFT Architecture using FIR Filter Structure......Page 314
Exercises......Page 319
References......Page 321
7.1 Introduction......Page 323
7.2.1 Basics......Page 324
7.2.2 Cut-set Retiming......Page 325
7.2.5 Re-pipelining: Pipelining using Feedforward Cut-set......Page 326
7.2.6 Cut-set Retiming of a Direct-form FIR Filter......Page 328
7.2.7 Pipelining using the Delay Transfer Theorem......Page 331
7.2.8 Pipelining Optimized DFG......Page 333
7.2.11 Mathematical Formulation of Retiming......Page 334
7.2.12 Minimizing the Number of Registers and Critical Path Delay......Page 336
7.2.13 Retiming with Shannon Decomposition......Page 337
7.3.1 Definitions......Page 338
7.3.2 Cut-set Retiming for a Feedback System......Page 341
7.4.1 Basics......Page 342
7.4.3 C-slow for FPGAs and Time-multiplexed Reconfigurable Design......Page 345
7.5 Look-ahead Transformation for IIR filters......Page 346
7.6 Look-ahead Transformation for Generalized IIR Filters......Page 348
7.7 Polyphase Structure for Decimation andInterpolation Applications......Page 349
7.8 IIR Filter for Decimation and Interpolation......Page 351
Exercises......Page 358
References......Page 362
8.1 Introduction......Page 365
8.3.1 Nyquist Sampling Theorem and Design Options......Page 366
8.3.2 Software-defined Radio Architecture and Band-pass Sampling......Page 367
8.3.3 A/D Converter Bandwidth and Band-pass Sampling......Page 369
8.4.1 Loop Unrolling......Page 370
8.4.2 Unfolding Transformation......Page 371
8.4.3 Loop Unrolling for Mapping SW to HW......Page 372
8.4.4 Unfolding to Maximize Use of a Compression Tree......Page 374
8.4.5 Unfolding for Effective Use of FPGA Resources......Page 375
8.4.6 Unfolding and Retiming in Feedback Designs......Page 378
8.5 Folding Techniques......Page 384
8.5.2 Folding Regular Structured DFGs......Page 385
8.5.3 Folded Architectures for FFT Computation......Page 388
8.5.4 Memory-based Folded FFT Processor......Page 389
8.5.5 Systolic Folded Architecture......Page 392
8.6 Mathematical Transformation for Folding......Page 394
8.7 Algorithmic Transformation......Page 398
Exercises......Page 399
References......Page 400
9.1 Introduction......Page 403
9.2.1 Bit-serial and Digit-serial Architectures......Page 404
9.2.2 Sequential Architecture......Page 405
9.3.1 Finite State Machines......Page 410
9.3.2 State Encoding: One-hot versus Binary Assignment......Page 412
9.3.3 Mealy and Moore State Machine Designs......Page 413
9.3.5 Coding Guidelines for Finite State Machines......Page 414
9.3.6 SystemVerilog Support for FSM Coding......Page 419
9.4.1 Basics......Page 420
9.4.2 Example: Design of a Four-entry FIFO......Page 421
9.4.3 Example: Design of an Instruction Dispatcher......Page 423
9.5 FSM Optimization for Low Power and Area......Page 430
9.6.1 Methodology......Page 431
9.6.2 Coverage Metrics for Design Validation......Page 432
9.7.1 Switching Power......Page 433
9.7.2 Clock Gating Technique......Page 434
9.7.3 FSM Decomposition......Page 435
Exercises......Page 437
References......Page 441
10.1 Introduction......Page 443
10.2.1 Basics......Page 444
10.2.2 Moore Micro-programmed State Machines......Page 447
10.2.3 Example: LIFO and FIFO......Page 448
10.3.1 Basics......Page 449
10.3.2 Loadable Counter-based State Machine......Page 451
10.3.3 Counter-based FSM with Conditional Branching......Page 452
10.3.4 Register-based Controllers......Page 453
10.3.6 Example to Illustrate Complete Functionality......Page 454
10.4 Subroutine Support......Page 456
10.5 Nested Subroutine Support......Page 457
10.6 Nested Loop Support......Page 458
10.7.1 Design for Motion Estimation......Page 461
10.7.2 Design of a Wavelet Processor......Page 465
Exercises......Page 468
References......Page 473
11.2.1 System Identification......Page 475
11.2.3 Acoustic Noise Cancellation......Page 476
11.3.1 Basics......Page 477
11.3.2 Least Mean Square (LMS) Algorithm......Page 478
11.4.1 Theory......Page 479
11.4.2 Example: NLMS Algorithm to Update Coefficients......Page 480
11.5.1 Acoustic Echo Canceller......Page 485
11.6.1 Basics......Page 486
11.6.2 Example: LEC Micro-coded Accelerator......Page 487
11.6.3 Address Registers Arithmetic......Page 496
11.6.4 Pipelining Options......Page 500
11.6.5 Optional Support for Coefficient Update......Page 501
11.6.7 Compression Tree and Single CPA-based Design......Page 502
Exercises......Page 503
References......Page 504
12.1 Introduction......Page 505
12.2 Direct Digital Frequency Synthesizer......Page 506
12.3 Design of a Basic DDFS......Page 507
12.4.1 Introduction......Page 508
12.4.2 CORDIC Algorithm for Hardware Implementation......Page 511
12.4.3 Hardware Mapping......Page 514
12.4.4 Time-shared Architecture......Page 520
12.4.5 C-slowed Time-shared Architecture......Page 523
12.4.7 Recoding of Binary Representation as ±1......Page 524
12.5.1 Introduction......Page 528
12.5.2 Hardware Optimization......Page 532
12.5.3 Novel Optimal Hardware Design......Page 536
Exercises......Page 541
References......Page 542
13.1 Introduction......Page 543
13.2.1 Bus-based Design......Page 544
13.2.3 Network-based Design......Page 545
13.2.6 KPN with Shared Bus and DMA Controller......Page 546
13.2.7 Network-on-Chip Top-level Design......Page 549
13.2.8 Design of a Router for NoC......Page 554
13.2.9 Run-time Reconfiguration......Page 556
13.2.10 NoC for Software-defined Radio......Page 557
13.3.2 Data Compression......Page 558
13.3.3 Encryption......Page 563
13.3.4 Channel Coding......Page 581
13.3.5 Framing......Page 583
13.3.6 Modulation......Page 584
13.3.7 Digital Up-conversion and Mixing......Page 594
13.3.8 Front End of the Receiver......Page 595
Exercises......Page 596
References......Page 599
Index......Page 601