Design principles for embedded systems

Preface
Acknowledgments
About This Book
Contents
About the Author
1 The Strategy
	1.1 Definition
	1.2 Common Characteristics
	1.3 Some Quality Metrics in ES Design
	1.4 Versatility Factors for ES Product
		1.4.1 Case Study: 1-1
	1.5 Technologies Involved
		1.5.1 Processors
		1.5.2 Platforms
		1.5.3 Devices-IC Technology
	1.6 Hardware/Software Co-design
	1.7 Summary
	1.8 Further Reading
	1.9 Exercises
	References
2 Use Cases
	2.1 History
		2.1.1 What Are Use Cases?
		2.1.2 Casual Versus Structured Version
		2.1.3 Black Box Versus White Box
		2.1.4 Hub and Spoke Model
	2.2 Details of the Use Case Model Entities
		2.2.1 Actor
		2.2.2 Stakeholder
		2.2.3 Primary Actor
		2.2.4 Supporting Actor
		2.2.5 Scope
		2.2.6 Scenarios
		2.2.7 Levels
		2.2.8 Use Case Entities and Their Relation
		2.2.9 When Are We Done?
		2.2.10 Standard Use Case Template
	2.3 Best Practices
	2.4 Summary
	2.5 Further Reading
	2.6 Exercises
	References
3 Models and Architectures
	3.1 Representation of a Design
		3.1.1 Behavioral Representation
		3.1.2 Structural Representation
		3.1.3 Physical Representation
		3.1.4 What Is a Model?
		3.1.5 Case Study: 3-1
		3.1.6 What Is Architecture?
		3.1.7 Relation Between Model and Architecture
	3.2 Model Taxonomy
		3.2.1 State-Oriented Models
		3.2.2 Activity-Oriented Models
		3.2.3 Structure-Oriented Models
		3.2.4 Data-Oriented Models
		3.2.5 Heterogeneous Models
	3.3 Finite-State Machine (Mealy) Model
		3.3.1 Finite-State Machine (Moore Model)
		3.3.2 Finite-State Machine with Data Path (FSMD)
		3.3.3 Case Study: 3-2
		3.3.4 Case Study: 3-3
		3.3.5 Summary: Finite-State Machines
	3.4 Petri Nets
		3.4.1 Modeling of System Characteristics by Petri Nets
		3.4.2 Properties of Petri Nets
		3.4.3 Case Study: 3-4
		3.4.4 Case Study: 3-5
		3.4.5 Summary: Petri Nets
	3.5 Hierarchical Concurrent FSMs
		3.5.1 Summary: HCFSM
		3.5.2 Case Study: 3-6
	3.6 Activity-Oriented Data Flow Graphs
		3.6.1 Case Study: 3-7
		3.6.2 Solution
		3.6.3 Summary: Data Flow Model
	3.7 Control Flow Graphs (Flowchart)
		3.7.1 Summary: CFG
	3.8 Structure-Oriented Models
		3.8.1 Summary: Structure Diagrams
	3.9 Data-Oriented Entity-Relationship Model
		3.9.1 Case Study: 3-8
	3.10 Jackson’s Structured Programming Model
		3.10.1 Summary: Jackson’s Model
	3.11 Heterogeneous Models
		3.11.1 Control/Data Flow Graph (CDFG)
		3.11.2 Summary: CDFG
		3.11.3 Case Study: 3-9
		3.11.4 Object-Oriented Model
		3.11.5 Encapsulation
		3.11.6 Inheritance
		3.11.7 Polymorphism
		3.11.8 Case Study: 3-10
		3.11.9 Case Study: 3-11
		3.11.10 Program State Machines
		3.11.11 Communication in PSM
		3.11.12 Case Study: 3-12
	3.12 Summary: Models and Architectures
	3.13 Further Reading
	3.14 Exercises
	References
4 Specification Languages: SystemC
	4.1 An Example
	4.2 Characteristics of ESL for Embedded Systems
		4.2.1 Concurrency
		4.2.2 Data-Driven
		4.2.3 Control Flow Driven
		4.2.4 Hierarchy of Behaviors
		4.2.5 Completion of Behaviors
		4.2.6 Shared Communication
		4.2.7 Synchronization
		4.2.8 Exception Handling
		4.2.9 Summary: Specification Languages
	4.3 SystemC
		4.3.1 What Is SystemC?
		4.3.2 SystemC Features
		4.3.3 SystemC 2.0 Language Architecture
		4.3.4 Module
		4.3.5 Module Declaration
		4.3.6 Module Ports
		4.3.7 Module Constructor
		4.3.8 Module Signals
		4.3.9 Positional Connection
		4.3.10 Named Connection
		4.3.11 Member Functions
	4.4 Processes
		4.4.1 Method (SCMETHOD)
		4.4.2 Thread (SCTHREAD)
	4.5 Case Study: 4.1
		4.5.1 Solution
		4.5.2 Half-Adder Module
		4.5.3 Full-Adder Module
		4.5.4 Driver Module
		4.5.5 Monitor Module
		4.5.6 The Test Bench
	4.6 Case Study: 4.2
	4.7 Objects in SystemC
		4.7.1 Scclock
		4.7.2 Data Types
		4.7.3 Wait Until
		4.7.4 ScStart
		4.7.5 ScEvent
		4.7.6 Wait
	4.8 Models of Computation in SystemC
		4.8.1 Untimed Functional Model
		4.8.2 Timed Functional Model
		4.8.3 Transaction-Level Model
		4.8.4 Behavior Hardware Model
		4.8.5 Register-Transfer Level Model
	4.9 Interface
	4.10 Channel
		4.10.1 Primitive Channels
		4.10.2 Hierarchical Channels
	4.11 Summary: SystemC
	4.12 Further Reading
	4.13 Exercises
	References
5 UML for Embedded Systems
	5.1 Motivation
	5.2 Typical Tasks and Roles in System Engineering
	5.3 UML Diagrams
	5.4 Structural Diagrams
		5.4.1 Class Diagram
		5.4.2 Association
		5.4.3 Association Class
		5.4.4 Case Study 1
		5.4.5 Aggregation
		5.4.6 Composition
		5.4.7 Generalization
		5.4.8 Case Study 2
		5.4.9 Interface
		5.4.10 Signals
		5.4.11 Component
		5.4.12 Deployment Diagram
	5.5 Behavioral Diagrams
		5.5.1 Use Case Diagram
		5.5.2 State Diagram
		5.5.3 Activity Diagram
		5.5.4 Sequence Diagram
		5.5.5 Case Study 4
	5.6 Other Diagrams
	5.7 Summary—UML
	5.8 Further Reading
	5.9 Exercises
	References
6 Real-Time Systems
	6.1 Definition and Examples
		6.1.1 A Digital Controller
	6.2 Broad Classification of RTS
		6.2.1 Periodic
		6.2.2 Mostly Periodic
		6.2.3 Aperiodic but Predictable
		6.2.4 Asynchronous and Unpredictable
	6.3 Terms in RT Systems
		6.3.1 Hard RT Systems
		6.3.2 Soft RT Systems
		6.3.3 Scheduler
		6.3.4 Preemptivity
		6.3.5 Criticality
		6.3.6 Laxity Function
	6.4 Periodic Schedule
		6.4.1 Modeling Periodic Tasks
		6.4.2 Task Utilization
		6.4.3 Response to External Events
	6.5 Precedence Constraints and Dependencies
		6.5.1 Precedence Graph
		6.5.2 Task Graph
		6.5.3 Task Dependencies
		6.5.4 Resource Graph
		6.5.5 Scheduling Process
		6.5.6 Valid and Feasible Schedule
	6.6 Scheduling Algorithms–Classification
		6.6.1 Static Scheduling
		6.6.2 Dynamic Scheduling
		6.6.3 Static Priority Scheduling
		6.6.4 Dynamic Priority Scheduling
	6.7 Clock-Driven Scheduling
		6.7.1 Notation
		6.7.2 Pseudo Algorithm
		6.7.3 Slack Time
		6.7.4 Handling Sporadic Jobs in Clock-Driven Scheduling
		6.7.5 Merits and Demerits
	6.8 Priority-Driven Periodic Tasks
		6.8.1 Rate Monotonic Algorithm (RMA)
		6.8.2 Deadline-Monotonic (DM) Algorithm
	6.9 Dynamic Priority Algorithms
		6.9.1 Earliest Deadline First (EDF)
		6.9.2 Least Slack Time First Algorithm (LST)
		6.9.3 Case Study 1
		6.9.4 Case Study-2
		6.9.5 Case Study 3
	6.10 Scheduling Sporadic Jobs
	6.11 Resource Access and Contention
		6.11.1 Priority Inversion
		6.11.2 Priority Inheritance
	6.12 Summary
	6.13 Further Reading
	6.14 Exercises
	References
7 Real-Time Operating Systems (RTOS)
	7.1 Introduction
	7.2 RTOS Concepts
		7.2.1 Task and Task States
		7.2.2 RTOS—Basic Organization
		7.2.3 Re-entrancy
		7.2.4 Semaphore
		7.2.5 Mutex
	7.3 Basic Design Using RTOS
		7.3.1 Case Study 1
	7.4 Concept-Process and Threads
		7.4.1 Kernel
		7.4.2 Process
		7.4.3 Thread
	7.5 Posix
	7.6 pThreads
		7.6.1 Create Thread
		7.6.2 Thread Synchronization
		7.6.3 Cancel Thread
		7.6.4 Schedule Threads
	7.7 Thread Synchronization
		7.7.1 Mutex
		7.7.2 Semaphore
		7.7.3 Condition Variable
		7.7.4 Reader’s/Writers Lock
		7.7.5 Spin Locks
		7.7.6 Barrier
	7.8 Design Strategies
		7.8.1 Master–Slave
		7.8.2 Thread per Client
		7.8.3 Thread per Request
		7.8.4 Work Queue
		7.8.5 Pipeline
	7.9 Summary RTOS
	7.10 Further Reading
	7.11 Exercises
	References
8 Networked Embedded Systems (NES)
	8.1 Introduction
	8.2 Characteristics
		8.2.1 Design Aspects
	8.3 Broad Segments of NES
		8.3.1 Automotive NES
		8.3.2 NES in Industrial Automation
		8.3.3 NES in Building Automation
		8.3.4 Wireless Sensor Networks (WSN)
	8.4 Automotive NES
		8.4.1 Event-Triggered Protocols
		8.4.2 Time Triggered Protocols (TT)
		8.4.3 Example TT Protocols
		8.4.4 Fundamental Services of TT Protocol
	8.5 CAN (Controller Area Network)
		8.5.1 CAN Frame
		8.5.2 CAN Messages
		8.5.3 CAN Physical Layer
		8.5.4 CAN Media Access and Arbitration
		8.5.5 CAN Protocol Stack
		8.5.6 CAN Information Exchange
	8.6 Time-Triggered CAN (TTCAN)
	8.7 NES in Industrial Automation
		8.7.1 Network Hierarchy
		8.7.2 Fieldbus
		8.7.3 Fieldbus Topology
	8.8 NES in Building Automation
		8.8.1 BACNET—Building Automation and Control Network
		8.8.2 LON Works
		8.8.3 ZigBee
	8.9 Wireless Sensor Networks (WSN)
		8.9.1 Structure
	8.10 Summary-NES
	8.11 Further Reading
	References
9 Human Interaction with Embedded Systems
	9.1 Motivation
	9.2 Overview
		9.2.1 Study Users for Good Interface
		9.2.2 Evaluate the Design
	9.3 Human System
		9.3.1 Vision
		9.3.2 Touch
		9.3.3 Movement
		9.3.4 Memory
		9.3.5 Cognitive System
	9.4 Physical System
		9.4.1 Handwriting Recognition
		9.4.2 Speech Recognition
		9.4.3 Eye Gaze
		9.4.4 Virtual Reality
		9.4.5 Sensing Position in 3D Space
		9.4.6 Augmented Reality (AR)
	9.5 Interaction Concepts
		9.5.1 Interaction Model
		9.5.2 Donald Norman’s Model
		9.5.3 Case Study-1
		9.5.4 Ergonomics
		9.5.5 Physical Design
	9.6 Recent Paradigms in Computer Interaction
		9.6.1 Metaphors
		9.6.2 Multimodality
		9.6.3 System Supported Cooperative Work
		9.6.4 Human–Agent Interaction
		9.6.5 Ubiquitous Computing
		9.6.6 Implicit Interface
	9.7 Design for Usability
		9.7.1 Goals of Usability Engineering
		9.7.2 Design Patterns
	9.8 Evaluation
		9.8.1 Cognitive Walkthrough
		9.8.2 Heuristic Evaluation
		9.8.3 Evaluation Through User Participation
		9.8.4 Model-Based Evaluation
		9.8.5 Case Study-3
	9.9 Summary
	9.10 Further Reading
	9.11 Exercises
	References
10 HW-SW Co-design
	10.1 Introduction
	10.2 Factors Driving Co-design
	10.3 Co-design Problems
	10.4 Conventional Model for HW-SW Design Process
	10.5 Integrated Co-design Process
	10.6 System Partitioning
	10.7 Partitioning Algorithms
	10.8 Summary
	10.9 Further Reading
	10.10 Exercises
	References
11 Energy Efficient Embedded Systems
	11.1 Introduction
		11.1.1 Activity Allocation
		11.1.2 Activity Mapping
		11.1.3 Activity Scheduling
		11.1.4 Energy Management
	11.2 Energy Dissipation in Devices
		11.2.1 Power Efficiency
	11.3 Techniques for Energy Minimization
		11.3.1 Dynamic Power Management (DPM)
		11.3.2 Dynamic Voltage Scaling (DVS)
		11.3.3 DVFS in Heterogeneous Processing Elements (PEs)
	11.4 Energy-Aware Scheduling
		11.4.1 Case Study-1
		11.4.2 Static DVFS Scheduling
		11.4.3 Case Study-2
	11.5 Advanced Configuration and Power Interface (ACPI)
		11.5.1 ACPI Components
		11.5.2 ACPI System
		11.5.3 ACPI System States
	11.6 Typical Guidelines for Power Management
		11.6.1 Power Management at Design Time
		11.6.2 Power Management at Run Time
	11.7 Summary
	11.8 Further Reading
	11.9 Exercises
	References
12 Embedded Processor Architectures
	12.1 Introduction
	12.2 Memory Hierarchy
	12.3 Cache Basics
		12.3.1 Direct Mapped Cache
		12.3.2 Fully Associative Cache
		12.3.3 Set Associative Cache
		12.3.4 Writing to Cache
		12.3.5 Replacing a Block During Cache Miss
		12.3.6 Basic Cache Optimizations
	12.4 Virtual Memory
		12.4.1 Case Study-1
		12.4.2 Few Techniques for Cache Performance
		12.4.3 Compiler Optimizations
	12.5 RISC Processors
		12.5.1 Instruction Cycle for RISC
	12.6 Pipelining
		12.6.1 Hazards in Pipelining
		12.6.2 Pipeline in MIPS Processor
		12.6.3 Pipeline in Arm Cortex-A8
	12.7 Data-Level Parallelism
		12.7.1 Vector Architectures
		12.7.2 Basic Structure
		12.7.3 Vector Instructions
		12.7.4 Lanes
		12.7.5 Vector Length Register
		12.7.6 Vector Mask Registers
		12.7.7 Memory System and Memory Banks
		12.7.8 Stride
		12.7.9 Gather–Scatter
	12.8 SIMD Architecture
	12.9 Graphic Processing Units (GPU) SIMT Architecture
		12.9.1 Programming Model
	12.10 Thread-Level Parallelism (TLP)
		12.10.1 Multicore Processor with Shared Memory
		12.10.2 Multi-processor System with Distributed Memory
		12.10.3 Multi-threaded Execution
	12.11 Reconfigurable Computing—FPGAs
		12.11.1 Generic PLD Architecture
		12.11.2 Generic FPGA Architecture
		12.11.3 Dynamic Configuration of FPGA
		12.11.4 System on Chip with FPGA
		12.11.5 Typical Mapping Flow of FPGA
		12.11.6 Logic Design with CLB
		12.11.7 Case Study–2
		12.11.8 Connectivity Programming
		12.11.9 Exploiting Reconfigurability
	12.12 Summary
	12.13 Further Reading
	12.14 Exercises
	References
13 Embedded Platform Architectures
	13.1 Introduction to Bus
	13.2 Data Transfers
		13.2.1 Synchronous Transfers
		13.2.2 Asynchronous Transfers
		13.2.3 Burst Transfers
		13.2.4 IO Addressing
	13.3 Typical ARM Platform with AMBA Bus
		13.3.1 Advanced High-Performance Bus
	13.4 Generic Interrupt Controller (GIC)
	13.5 Modern IO Interfaces
		13.5.1 Universal Serial Bus (USB)
		13.5.2 Bluetooth
		13.5.3 Low-Performance Device Interconnects
	13.6 IOT Platform for Embedded Systems
		13.6.1 Privacy in IoT
		13.6.2 Security in IoT
		13.6.3 IoT Architecture
		13.6.4 Communication in IoT
	13.7 Summary
	13.8 Exercises
	13.9 Further Study
	References
14 Security in Embedded Systems
	14.1 Motivation
	14.2 Introduction
		14.2.1 Terminology
		14.2.2 Cyber-Attacks on Embedded Systems
		14.2.3 Security Policies
	14.3 Security Vulnerabilities in ES
		14.3.1 Buffer Overflow
		14.3.2 Improper Input Data Validation
		14.3.3 Improper Authentication
		14.3.4 Out of Bounds Memory Access
		14.3.5 DMA Attacks
		14.3.6 Platform Reset Attacks
	14.4 Basic Security Algorithms
		14.4.1 Symmetric Ciphers
		14.4.2 Secure Hash Algorithms
		14.4.3 Asymmetric Algorithms
	14.5 Security Protocols for Embedded Systems
	14.6 Guidelines for Secure Systems
		14.6.1 Trust Across Devices
		14.6.2 Secure Firmware Updates and Critical Data
		14.6.3 Secure Boot
		14.6.4 UEFI Security Guidance
		14.6.5 Trusted Zone
		14.6.6 Secure OS
		14.6.7 Secure Storage and Memory
		14.6.8 System Recovery
		14.6.9 Security Life Cycle
	14.7 Security Standards for Embedded Systems
		14.7.1 Digital Rights Management
		14.7.2 Fast Identity Online Alliance (FIDO)
	14.8 Typical Secured Platform Architecture
	14.9 Summary
	14.10 Further Reading
	14.11 Exercises
	References
Index