Wireless Interface Technologies for 3D IC and Module Integration

Cover
Half-title
Title page
Copyright information
Contents
Preface
1 Introduction: 3D Integration and Near-Field Coupling
	1.1 A Short History of the Computer, IC, and Connector
		1.1.1 History of the Computer
		1.1.2 The Four Seasons of IC Development
			1.1.2.1 The ''Big Bang'': Invention of the IC
			1.1.2.2 Spring: Explosive Growth through Scaling
			1.1.2.3 Summer: The Power Wall
			1.1.2.4 Fall: The Leakage Wall
			1.1.2.5 Winter: The End of Scaling?
			1.1.2.6 The Second Spring
		1.1.3 History of the Connector
			1.1.3.1 The Solderless Connection
			1.1.3.2 Recent Challenges for the Connector
		1.1.4 Closing Thoughts
	1.2 Energy-Efficient Computing
		1.2.1 High-Performance IC
		1.2.2 Low-Power IC
		1.2.3 Low-Power IC Interface
		1.2.4 Energy-Efficient IC
		1.2.5 Energy-Efficient Computing Trends
		1.2.6 Closing Thoughts
	1.3 Evolution from 2D to 3D Integration
		1.3.1 Motivation for 3D Integration
		1.3.2 Monolithic 3D IC
		1.3.3 Conventional 3D Integration Solutions
		1.3.4 Advanced 3D Integration Solutions
			1.3.4.1 Nature of a TSV
			1.3.4.2 TSV for Wired IC Integration
			1.3.4.3 2.5D IC Integration Using TSV
			1.3.4.4 Wireless 3D Integration
			1.3.4.5 Inductive vs. Capacitive Coupling for 3D Integration
			1.3.4.6 Wireless 3D Integration
		1.3.5 Closing Thoughts
	1.4 Near-Field Coupling Interconnect Technology
		1.4.1 Motivation for Using Near-Field Coupling for Interconnection
		1.4.2 Near-Field IC Interconnect Technology
			1.4.2.1 Motivation for a Near-Field IC Interface
			1.4.2.2 Characteristics and Merits of TCI
			1.4.2.3 Application of TCI
		1.4.3 Near-Field Module Connector Technology
			1.4.3.1 Motivation for a Near-Field Coupled Module Connector
			1.4.3.2 Characteristics and Merits of TLC Technology
			1.4.3.3 Application of TLC
		1.4.4 Closing Thoughts
	References
2 ThruChip Interface: A Wireless Chip Interface
	2.1 TCI Fundamentals
		2.1.1 Basic Structure and Operating Principle
		2.1.2 Transceiver Design
			2.1.2.1 Standard Transceiver Design
			2.1.2.2 Transceiver Characteristics
		2.1.3 Coil Design
			2.1.3.1 Coil Layout Options
			2.1.3.2 Coil Design Parameters and Electrical Characteristics
		2.1.4 Crosstalk between Channels
		2.1.5 Electromagnetic Compatibility
		2.1.6 Closing Thoughts
	2.2 TCI Design Trade-offs and Optimization
		2.2.1 Design Solution Space
		2.2.2 Design for Power Efficiency
			2.2.2.1 Low VDD Transmitter Design: NMOS Push-Pull Transmitter
			2.2.2.2 Pulse Transmitter Design
			2.2.2.3 SerDes for High Per-Channel Data Rate
			2.2.2.4 Sleep Mode
		2.2.3 Design for Area Efficiency
			2.2.3.1 PDM: Phase Division Multiplexing
			2.2.3.2 Coil Size
		2.2.4 Implementation Examples
			2.2.4.1 Design for Low Power
			2.2.4.2 Design for High Data Rate
			2.2.4.3 Design for High-Density and High-Interface Bandwidth
		2.2.5 Closing Thoughts
	2.3 TCI 3D/2.9D/2.5D/2D IC Integration
		2.3.1 TCI-Enhanced 3D IC Integration: Processor + SRAM
		2.3.2 TCI-Enhanced 2.9D IC Integration
		2.3.3 TCI-Enhanced 2.5D IC Integration
		2.3.4 TCI-Enhanced 2D IC Integration
		2.3.5 Closing Thoughts
	2.4 Wireless Power Delivery
		2.4.1 Basic Structure of a Wireless Power Interface
		2.4.2 Optimization for Efficiency and Quality
			2.4.2.1 Enhanced NCG Rectifier for Efficiency
			2.4.2.2 Half-Wave Rectifier for Efficiency
			2.4.2.3 Multichannel, Multiphase for Increased Power and Reduced Ripple
			2.4.2.4 Nested Clover Coils for Reduced Interference of Data Channel
			2.4.2.5 Load Tracking for Dynamic Transmit Power Control
		2.4.3 Example Application: A Digital Rosetta Stone
		2.4.4 Closing Thoughts
	2.5 Highly Doped Silicon Via (HDSV)
		2.5.1 HDSV Fabrication
		2.5.2 HDSV Characterization
		2.5.3 Closing Thoughts
	2.6 Wideband DRAM Interface
		2.6.1 Prototype TCI Wideband DRAM System
			2.6.1.1 Architecture
			2.6.1.2 Transceiver Design
		2.6.2 Case Study: Area Saving vs. TSV-HBM
		2.6.3 Closing Thoughts
	2.7 Stacked Flash Memory
		2.7.1 Stacking and Communication Schemes
		2.7.2 Area Efficiency Optimization
		2.7.3 Closing Thoughts
	2.8 3D Network-on-Chip (NoC)
		2.8.1 Interplane Network Design for TCI 3D NoC
		2.8.2 Unidirectional Ring Network with Bubble Flow Control
		2.8.3 Dynamically Reconfigurable Bidirectional Ring Network with Bubble Flow Control
		2.8.4 Escalator Network with Piggyback Flow Control
		2.8.5 Closing Thoughts
	2.9 Postscript: Parallel TCI Research
		2.9.1 Coil Design Methodology
		2.9.2 Application of TCI to Heterogeneous 3D IC Integration
	2.10 Postscript: The Phenomenon of Coupled Resonation
	References
3 Transmission Line Coupler: A Wireless Module Connector
	3.1 TLC Fundamentals
		3.1.1 Basic Structure and Operating Principle
		3.1.2 Electrical Characteristics and Design Parameters
		3.1.3 Transceiver Design
			3.1.3.1 Transmitter Design
			3.1.3.2 Receiver Design
		3.1.4 Closing Thoughts
	3.2 TLC Multidrop Bus
		3.2.1 EE-TLC for Master-Slave, Multi-Drop Bus
		3.2.2 Single-Ended to Differential Conversion TLC (SDC-TLC)
		3.2.3 BD-TLC for Multimaster, Multidrop Bus
			3.2.3.1 BD-TLC Coupler Design
			3.2.3.2 BD-TLC Transceiver Design
		3.2.4 Case Study: TLC in Satellite Processor Systems
		3.2.5 Closing Thoughts
	3.3 TLC for Smartphone
		3.3.1 Small Footprint TLC Derivatives for Smartphone
			3.3.1.1 VD-TLC for Simultaneous Dual Channel Transmission
			3.3.1.2 T-TLC for Extended Communication Distance
		3.3.2 Smartphone TLC Transceiver with High EMC Immunity
			3.3.2.1 Edge-Counting CDR for High Noise Immunity
		3.3.3 Smartphone TLC Experimental Results
		3.3.4 Closing Thoughts
	3.4 TLC for Automotive LAN
		3.4.1 EM-Clip: Twisted Pair TLC Derivative
		3.4.2 Automotive TLC Transceiver with High EMC Immunity
			3.4.2.1 Oversampling Manchester Coding
			3.4.2.2 Correlator-Based, High Noise Immunity CDR
		3.4.3 Automotive TLC Experimental Results
		3.4.4 Closing Thoughts
	3.5 TLC SSD
		3.5.1 System Architecture
		3.5.2 Wireless Data Interface
		3.5.3 Wireless Power Interface
		3.5.4 System-Level Challenges and Solutions
			3.5.4.1 System Startup Sequence
			3.5.4.2 Wireless Interface Error Correction
		3.5.5 Closing Thoughts
	References
4 The Future of Computing: 3D SRAM for Neural Network, eBrain
	4.1 Neural Net Accelerator on TCI 3D-SRAM
		4.1.1 The DNN Inference Engine
		4.1.2 The TCI SRAM Stack
		4.1.3 Performance Analysis
	4.2 FPGA on TCI 3D-SRAM: An Electronic Right Brain
		4.2.1 Structural Comparison between an Electronic Left and Right Brain
		4.2.2 Construction of an Electronic Right Brain
		4.2.3 FPGA Right-Brain Performance Leaps Enabled by TCI 3D-SRAM
	4.3 eBrain: A True Electronic Brain
		4.3.1 Construction of an eBrain
		4.3.2 A Palmtop eBrain
	4.4 Closing Thoughts: Predicting the Future of Computing
		4.4.1 Recent Trends in Computing
		4.4.2 Recent Trends in the IC Industry
		4.4.3 Role of TCI and TLC Wireless Interfaces
		4.4.4 A Future of Digital Inclusion
	References
Index