VLSI: Integrated Systems on Silicon: IFIP TC10 WG10.5 International Conference on Very Large Scale Integration 26–30 August 1997, Gramado, RS, Brazil

Front Matter....Pages i-xiii
Front Matter....Pages 1-1
A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computing....Pages 3-14
A VLSI architecture for real-time edge linking....Pages 15-26
VLSI Implementation of Contour Extraction from Real Time Image Sequences....Pages 27-38
Front Matter....Pages 39-39
An architecture for a 12 bits, low power integrated CMOS pressure sensor with thermal compensation....Pages 41-52
On-line testing of analog circuits by adaptive filters....Pages 53-64
A Multi-Mode Signature Analyzer for Analog and Mixed Circuits....Pages 65-76
Front Matter....Pages 77-77
An All-Digital Single-Chip Symbol Synchronizer and Channel Decoder for DVB....Pages 79-90
An ATM Switching Element with programmable capacity....Pages 91-102
Reconfigurable CPU Cache Memory Design: Fault Tolerance and Performance Evaluation....Pages 103-114
Front Matter....Pages 115-115
A Low-Voltage Operational Transconductance Amplifier and Its Application to a Bandpass Gm-C Filter....Pages 117-128
A Programmable Second Generation SI Integrator for Low-Voltage Applications....Pages 129-138
Low-voltage current-mode analogue continuous-time filters....Pages 139-150
A set of device generators for analogue and mixed-signal layout synthesis....Pages 151-162
Front Matter....Pages 163-163
E-TSPC: Extended True Single-Phase-Clock CMOS circuit technique....Pages 165-176
Noise and power programmability in semi-custom I/O buffers....Pages 177-188
Charge Pump DPLL to Operate at High Frequencies....Pages 189-200
A 3.3 Gb/s Sample Circuit with GaAs MESFET Technology and SCFL Gates....Pages 201-212
Front Matter....Pages 213-213
An Embedded Accelerator for Real World Computing....Pages 215-226
Design of a Low Power 108-bit Conditional Sum Adder Using Energy Economized Pass-transistor Logic (EEPL)....Pages 227-238
A novel globally asynchronous locally synchronous sliding window DFT implementation....Pages 239-250
Front Matter....Pages 213-213
Unfolded Redundant CORDIC VLSI Architectures With Reduced Area and Power Consumption....Pages 251-262
Front Matter....Pages 263-263
Multi-View Design of Asynchronous Micropipeline Systems using Rainbow....Pages 265-276
High Level Synthesis of Protocols Described by a Formal Description Technique....Pages 277-288
Matisse: a concurrent and object-oriented system specification language....Pages 289-300
Front Matter....Pages 301-301
Library Free Technology Mapping....Pages 303-314
An implicit formulation for exact BDD minimization of incompletely specified functions....Pages 315-326
Sequential Logic Optimization with Implicit Retiming and Resynthesis....Pages 327-338
Boolean Mapping based on Testing Techniques....Pages 339-350
Front Matter....Pages 351-351
Testability Analysis of Circuits using Data-Dependent Power Management....Pages 353-364
Data Sequencing for Minimum-transition Transmission....Pages 365-376
Spurious Transitions in Adder Circuits : Analytical Modelling and Simulations....Pages 377-388
Power Reduction Through Clock Gating by Symbolic Manipulation....Pages 389-399
Front Matter....Pages 401-401
A Timing-Driven Floorplanning Algorithm with the Elmore Delay Model for Building Block Layout....Pages 403-414
An Efficient Layout Style for Three-Metal CMOS Macro-Cells....Pages 415-426
Coupled Circuit-Interconnect Modeling and Simulation....Pages 427-438
Accurate static timing analysis for deep submicronic CMOS circuits....Pages 439-450
Front Matter....Pages 451-451
A Time Driven Adder Generator Architecture....Pages 453-463
User Guided High Level Synthesis....Pages 464-475
Empirical Interconnect Crosstalk Characterization for High Level Synthesis....Pages 476-487
Methods and tools for high and system level synthesis....Pages 488-500
Front Matter....Pages 501-501
A New Frequency-domain Analog Test Generation Tool....Pages 503-514
Boundary-Scan Testing for Mixed — Signal MCMs....Pages 515-525
Stress Testing: A Low Cost Alternative for Burn-in....Pages 526-539
Non-Monte Carlo Simulation and Sensitivity of Linear(ized) Analog Circuits under Parameter Variations....Pages 540-551
Top-Down Design Methodology & Technology for Microsystems....Pages 552-566
Back Matter....Pages 568-570