VLSI Implementations for Image Communications (Volume 2) (Advances in Image Communication, Volume 2)

Front Cover
VLSI Implementations for Image Communications
Copyright Page
Table of Contents
INTRODUCTION TO THE SERIES: \"Advances In Image Communication\"
Preface
Chapter 1. Video Coding Techniques: An Overview
	1. INTRODUCTION
	2. QUANTIZATION
	3. PREDICTIVE IMAGE CODING
	4. ENTROPY CODING
	5. ORTHOGONAL TRANSFORMS
	6. MOTION ESTIMATION/COMPENSATION
	7. SUBBAND PROCESSING
	8. VIDEO CODING EXAMPLES
	9. SUMMARY
	References:
Chapter 2. VLSI Implementation Strategies
	1. INTRODUCTION
	2. IMPLEMENTATION COST
	3. HARDWARE RELATED CHARACTERISTICS OF ALGORITHMS
	4. MULTIPROCESSOR ARCHITECTURES
	5. INTERACTION BETWEEN ALGORITHMS AND ARCHITECTURES
	6. CONCLUSION
	7. REFERENCES
Chapter 3. Mapping Algorithms onto VLSI Architectures
	1. Introduction
	2. The Design Problem
	3. Scheduling and Allocation
	4. A Methodology for Mapping Algorithms Onto Architectures
	5. Concluding Remarks
	References
Chapter 4. Multiprocessor DSPs for Low Bit Rate Video Codec
	1. Introduction
	2. Video coding requirements
	3. Multiprocessor DSP System for Video Codec
	4. DSP Architecture and Design
	5. A single board video codec using multiple IDSP
	6. Future trends in DSP
	7. References
Chapter 5. A Real-Time Parallel Processor for Video Signal Processing
	1. INTRODUCTION
	2. VSP ARCHITECTURE
	3. VSPM STRUCTURE
	4. VIDEO PROCESSING SYSTEMS
	5. CONCLUSION
	6. REFERERENCES
Chapter 6. High Throughput Digital Filters
	1. Introduction
	2. Transversal Filters
	3. Special Transversal Filters
	4. Parallelization and Time-Sharing - Matching the Troughput Requirements
	5. Recursive Filters
	6. Programmable Two-Dimensional Transversal Filters
	7. Concluding Remarks
	References
Chapter 7. Orthogonal Transforms
	1. INTRODUCTION
	2. THE DISCRETE COSINE TRANSFORM : ALGORITHMIC VIEWPOINT
	3. THE DISCRETE COSINE TRANSFORM : ARCHITECTURAL VIEWPOINT
	4. ARCHITECTURE OF A DCT PROCESSOR: AN EXAMPLE
	5. CONCLUSION
	6. ACKNOWLEDGEMENTS
	7. REFERENCES
Chapter 8. Algorithms and VLSI Architectures for Motion Estimation
	1. INTRODUCTION
	2. MOTION ESTIMATION ALGORITHMS
	3. VLSI ARCHITECTURES AND IMPLEMENTATIONS FOR BMA
	4. VLSI ARCHITECTURES AND IMPLEMENTATIONS FOR PRA
	5. CONCLUSION
	ACKNOWLEDGEMENT
	REFERENCES
Chapter 9. VLSI Architectures and Implementations for Vector Quantization
	1 Vector Quantization Algorithms
	2 Full Search Techniques
	3 Tree Search Schemes
	4 IC Design Strategy for VQ
	5 Summary
	References
Chapter 10. DPCM-Codecs
	1. INTRODUCTION
	2. DPCM ALGORITHMS
	3. VLSI ARCHITECTURES FOR 2D DPCM
	4. CIRCUIT TECHNIQUES FOR SPEEDUP OF DPCM IMPLEMENTATION
	5. REALIZATION TECHNIQUES FOR LINE DELAYS AND FORMATTERS
	6. FURTHER ASPECTS
	7. DESIGN EXAMPLES
	8. CONCLUSION
	REFERENCES
Chapter 11. Design of High-Throughput Entropy Codec
	1. INTRODUCTION
	2. ALGORITHM OVERVIEW AND SYSTEM CONSIDERATIONS
	3. ARCHITECTURES FOR THE VLD
	4. AN ENTROPY CODEC FOR HDTV APPLICATIONS
	5. OTHER TECHNIQUES FOR HIGH-SPEED IMPLEMENTATIONS
	6. CONCLUSION
	ACKNOWLEDGEMENT
	REFERENCES
Chapter 12. Parallel Processing and Pipelining in Huffmann Decoder
	1. Introduction
	2. Huffman Decoder using Finite State Machines
	3. Multiple Source Interleaved Decoder
	4. Table Look-Up Decoder
	5. Pipelined Decoder Using Look-Ahead
	6. Incremental Block Decoder
	7. Parallel and Pipelined Decoder using Look-Ahead
	8. Block Postcomputation Decoder
	9. Bit-Positioning Postcomputation
	10. Source Control Decoder
	11. Concurrent Loss-Less Coder
	12. Loss-Less Coder with Maximum Code Word Length
	13. Efficient Lossless Coder with Conditional Coding
	14. Conclusion
	15. Acknowledgement
	16. References
Subject Index