Understanding Signal Integrity

Understanding Signal Integrity......Page 2
Contents......Page 6
Preface......Page 16
1.2 The Importance of Signal Integrity: The First Transatlantic Telegraph Cable......Page 18
1.3 What Is a Pulse?......Page 20
1.4.2 Recreating a Pulse with Sine Waves......Page 21
1.4.3 Why Does the Frequency Domain Matter to Signal Integrity Engineers?......Page 22
1.4.4 Upper Bandwidth......Page 24
1.5.1 What Is Simultaneous Switching Noise?......Page 25
1.6 What Is the Dielectric Constant and Loss Tangent?......Page 26
References......Page 27
2.2 Why Perform a Signal Integrity Analysis?......Page 30
2.3 What Is a Typical Signal Integrity Workfl ow?......Page 31
2.4 Signal Integrity Worst-Case Analysis......Page 33
2.4.2 What Combination of Environmental Effects Are Worst Case?......Page 34
2.4.3 Using SI Analysis Results During Debug......Page 35
2.5 Main Points......Page 36
References......Page 37
3.2.1 What Are Transistor Level Models?......Page 38
3.2.2 What Are IBIS Models?......Page 39
3.3 Modeling Transmission Lines......Page 40
3.4.2 What Is Insertion Loss?......Page 41
3.5.1 What Are 2D Field Solvers?......Page 43
3.5.2 What Are 3D Field Solvers?......Page 44
References......Page 45
4.2 Test Boards......Page 48
4.2.1 Test Boards as a Chip Debug Platform......Page 49
4.3 Evaluation Boards......Page 50
4.4 Roll of the Printed Circuit Layout Shop......Page 51
4.6 Alternative Methods for Design and Fabrication......Page 52
References......Page 53
5.2.1 How Are Connections Made Between Layers?......Page 54
5.3 What Is the Significance of Calling a Circuit Board “FR4”?......Page 56
5.3.1 Why Is There Such Variability in Dk Between Laminate Manufacturers?......Page 57
5.3.3 What Are Some Alternatives to FR4?......Page 58
5.4 Circuit Board Traces......Page 59
5.4.3 What Is a Mil and What Does a Trace Thickness in Ounces Mean?......Page 60
5.4.5 What Is Surface Roughness and What Are Typical Values?......Page 62
5.5 Main Points......Page 63
Problems......Page 64
References......Page 65
6.2.1 What Is the Signal Return Path?......Page 66
6.3 Circuit Model of a Transmission Line......Page 67
6.4 Impedance and Delay......Page 68
6.5 How Does a Signal Travel Down the Line?......Page 69
6.6.1 How Does Current Flow in Return Paths That Are Not Ground?......Page 72
6.6.2 What Is the Behavior When One Return Path Is a Related Power Plane?......Page 73
6.6.3 How Does the Return Current Flow When the Power Supply Is Not theSignaling Voltage?......Page 74
6.7 When Does a Conductor, Via, or Connector Pin Act Like a Transmission Line?......Page 75
6.8 Main Points......Page 76
Problems......Page 77
References......Page 78
7.2 DC Resistance and Resistivity......Page 80
7.3 Stripline and Microstrip Capacitance......Page 81
7.3.1 What Is the Effective Dielectric Constant?......Page 82
7.3.2 What Are the Differences Between Microstrip and Stripline Capacitances?......Page 83
7.3.4 What Is Conductance and How Is It Determined?......Page 84
7.4 Stripline and Microstrip Inductance......Page 85
7.5.1 What Is the Proximity Effect?......Page 86
7.7 Understanding Stripline and Microstrip Impedance......Page 88
7.8.1 How Do the Dielectric and Effective Dielectric Constants Affect DelayTime?......Page 90
7.9 Main Points......Page 91
References......Page 93
8.2.1 What Effects Do Losses Have on Signals?......Page 96
8.2.2 How Is Loss Specified?......Page 97
8.3 What Creates Transmission Line Loss and How Is It Characterized?......Page 98
8.3.1 Loss Differences Between Microstrip and Stripline Traces......Page 99
8.4 How Do Impedance and Loop Resistance Affect Conductor Loss?......Page 100
8.4.1 How Does Surface Roughness Increase Conductor Loss?......Page 101
8.4.3 What Can Be Done to Reduce Conductor Losses?......Page 102
8.5 Understanding Dielectric Losses......Page 103
8.5.2 Effects of Temperature and Moisture......Page 104
8.6 Summary of Signal Loss and Distortion Characteristics......Page 105
8.9 Main Points......Page 106
Problems......Page 107
References......Page 108
9.2.1 What Are the Capacitance and Inductance Matrices?......Page 110
9.3 How Does Switching Alter the Trace Inductance and Capacitance?......Page 112
9.3.1 How Is the Capacitance Affected?......Page 113
9.3.2 How Is the Inductance Affected?......Page 114
9.4 What Effect Does Coupling Have on Impedance and Delay?......Page 115
9.5 What Are Odd and Even Modes?......Page 116
9.5.2 Why Is the Even- and Odd-Mode Timing the Same for Stripline But Notfor Microstrip?......Page 118
9.5.3 By How Much Does the Even- and Odd-Mode Impedance Change?......Page 119
9.7 How Is Receiver Timing Affected by In- and Out-of-Phase Switching?......Page 120
Problems......Page 122
References......Page 123
10.2 How Is Crosstalk Created and What Are Its Characteristics?......Page 124
10.3.1 Calculating FEXT......Page 126
10.3.2 What Are Typical Kf Values?......Page 128
10.4.1 Calculating NEXT......Page 129
10.4.2 What Are Typical Kb Values?......Page 131
10.5 How Closely Do Calculation and Simulation Agree?......Page 132
10.6 Guard Traces......Page 133
10.7 Main Points......Page 134
Problems......Page 136
References......Page 138
11.2 How Are Refl ections Created?......Page 140
11.3.1 What Determines the Reflection Coefficient Value?......Page 143
11.4.1 Difference Between the Response of a Pulse and a Step......Page 144
11.5 What Is the Behavior When There Are Multiple Refl ections?......Page 145
11.6 Reactive Discontinuities......Page 149
11.7 Main Points......Page 151
References......Page 152
12.2.1 Selecting the Resistance Value......Page 154
12.3 Parallel and Thevenin Termination......Page 156
12.3.1 Selecting Vtt and Vterm......Page 158
12.3.2 Thevenin Termination......Page 159
12.4 Diode Termination......Page 160
12.4.1 Diode Types......Page 161
12.5 AC Termination......Page 162
12.6.1 Single-Load Point-to-Point Termination......Page 163
12.6.2 Multiple Load Point-to-Point Termination......Page 165
12.7 Multidrop Lines......Page 167
12.7.1 Response When Signal Rise Time Is Very Short......Page 168
12.7.2 Response When Signal Rise Time Is Comparable to the TransmissionLine Delays......Page 169
12.8 Stubs and Branches......Page 171
12.8.1 Branches......Page 172
12.9 Main Points......Page 174
Problems......Page 175
References......Page 176
13.1 Introduction......Page 178
13.2 What Are the Electrical Characteristics of Differential Signaling?......Page 179
13.2.2 What Is an Eye Diagram?......Page 180
13.2.3 What Is Intersymbol Interference?......Page 181
13.3 What Are the Electrical Characteristics of a Differential Transmission Line?......Page 182
13.3.1 Why Is the Differential Impedance Twice the Odd-Mode Impedance?......Page 183
13.4 How Are Differential Transmission Lines Terminated?......Page 186
13.4.1 How Should a Diff-Pair Be Terminated When the Propagation Is Not Fully Odd Mode?......Page 187
13.5 How Are Differential Transmission Lines Created?......Page 189
13.5.1 Manufacturing Trade-Offs Between Loosely and Tightly Coupled Pairs......Page 190
13.6 What Are Some Suggested Diff-Pair Layout and Routing Rules?......Page 191
13.6.1 Obtaining the Proper Differential Impedance......Page 192
13.6.3 Keeping Signal Traces Far Away from Diff-Pairs......Page 193
13.6.5 Route on Same Layers......Page 194
13.6.9 Match Lengths on Each Layer......Page 195
13.6.10 Ensure That Noise Is Equally Coupled to Both Traces......Page 196
Problems......Page 198
References......Page 199
14.2 Mitered Corners......Page 202
14.3 Routing Near the Board Edge......Page 204
14.4 Serpentine Traces......Page 205
14.4.3 How Long Should the Segments Be?......Page 207
14.5.1 Via Circuit Model......Page 208
14.5.2 What Factors Determine Via Capacitance?......Page 209
14.5.5 What Are Nonfunctional Pads?......Page 210
14.5.7 What Are Differential Vias?......Page 211
References......Page 212
15.2 Questions to Ask When Reviewing PCB Stackup......Page 216
15.3 Questions to Ask When Reviewing Crosstalk Simulations......Page 218
15.4 Questions to Ask When Reviewing Signal Quality Simulations......Page 219
15.5 Questions to Ask When Reviewing Prelayout Simulations......Page 221
15.6 Questions to Ask When Reviewing Postlayout Simulations......Page 222
15.9 Questions to Ask When Reviewing ASIC Driver Selection Choices......Page 223
References......Page 224
16.2 Reducing Crosstalk......Page 226
16.3 Reducing Refl ections......Page 227
16.5 Improving Inadequate Timing Margins......Page 228
16.6 Correcting Intersymbol Interference (ISI)......Page 229
16.8 Options to Reduce Circuit Board Thickness......Page 230
16.9 Steps to Take When There Are Not Enough Routing Layers......Page 231
16.10 Steps to Take When a Circuit Board Must Be Cost Reduced......Page 232
References......Page 233
17.2 How to Convert from Decibel Loss to Signal Swing......Page 234
17.3 Estimating DC Resistance......Page 235
17.4 Finding Inductance and Capacitance When the Physical Dimensions Are Not Known......Page 236
17.6 Finding Stripline Inductance and Capacitance When Trace Geometry Is Known......Page 237
17.7.2 Microstrip Capacitance......Page 238
17.8.1 Inductance......Page 239
17.9 Calculating Trace Loss from a Circuit Model......Page 240
17.10.1 Dielectric Loss......Page 241
17.11.1 Dielectric Loss......Page 242
17.13 Finding Exposed Microstrip Impedance......Page 243
17.14 Finding Solder Mask Covered Microstrip Impedance......Page 244
17.15 Wavelength......Page 245
References......Page 246
About the Author......Page 248
Index......Page 250