Understanding Computer Organization A Guide to Principles Across RISC-V, ARM Cortex, and Intel Architectures

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1
	Preface
	Contents
	About the Author
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	1 Memory-Mapped Input/Output
		1.1 Introduction
		1.2 A Memory-Mapped Register
		1.3 Two Memory Mapped Registers
		1.4 Several Memory Mapped Registers
		1.5 Registers Mapped at Consecutive Addresses
		1.6 Partial Versus Full Address Decoding
		1.7 Case Study: Using the GPIO Interface in FE310-G002 RISC-V Based System-on-Chip
			1.7.1 Program GPIO in Assembly
			1.7.2 Program GPIO in C
		1.8 Case Study: Using the GPIO Interface in ARM Cortex-M Based …
			1.8.1 Cortex-M Fixed Memory Address Space
			1.8.2 GPIO Interface in STM32H7
			1.8.3 Functional Description of the GPIO Interface in STM32H7
			1.8.4 Program GPIO in C Using HAL
		1.9 Case Study: Using the UART Interface in FE310-G002 …
			1.9.1 Universal Asynchronous Receiver Transmitter
			1.9.2 The UART Interface in the SiFive FE310
			1.9.3 Program UART in C
			1.9.4 UART Pins
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	2 Interrupts and Interrupt Handling
		2.1 Introduction
		2.2 Why Having Interrupts?
		2.3 Interrupts
			2.3.1 Types of Interrupts
			2.3.2 Handling Interrupts
		2.4 ARM Cortex-M7 Interrupts
			2.4.1 ARM Cortex-M7 Programmer\'s Model
			2.4.2 System Control Block
			2.4.3 Exceptions
			2.4.4 Exception Numbers and Priorities
			2.4.5 Vector Table and Exception Handlers
			2.4.6 Exception Entry and Exit
			2.4.7 Case Study: A Simple Task Scheduler on ARM Cortex-M7
		2.5 RISC-V Interrupts and Exceptions
			2.5.1 RISC-V Privileged Modes
			2.5.2 RISC-V Machine Modes Exceptions
			2.5.3 FE-310 Interrupts
			2.5.4 Interrupt Entry and Exit
			2.5.5 Implementing Vector Table and Handlers
			2.5.6 Case Study: A Simple Task Scheduler on RISC-V Based FE310
		2.6 ARM 9 Exceptions and Interrupts
			2.6.1 Vector Table and Interrupt Priorities
			2.6.2 ARM9 Interrupt Handling
			2.6.3 Interrupt Handlers in C
		2.7 Intel Interrupts
		2.8 Interrupt Controllers
			2.8.1 ARM Advanced Interrupt Controller
			2.8.2 RISC-V Platform-Level Interrupt Controller in FE310
			2.8.3 ARM Cortex-M Nested Vectored Interrupt Controller
			2.8.4 Case Study: External Interrupts in STM32H7xx Microcontrollers
			2.8.5 Intel 8259A Programmable Interrupt Controler
			2.8.6 8259A PIC Cascading
			2.8.7 Intel Advanced Programmable Interrupt Controler
		2.9 PCI Interrupts
			2.9.1 PCI Legacy Interrupts
			2.9.2 PCI Interrupts Routing
			2.9.3 Message Signaled Interrupts
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	3 Direct Memory Access
		3.1 Introduction
		3.2 Programmed Input/Output
		3.3 Interrupt-Driven I/O
		3.4 Direct Memory Access
		3.5 Real-World DMA Controllers
			3.5.1 Intel 8237A DMA Controller
			3.5.2 STM32H7 Series DMA Controller
		3.6 Bus Mastering DMA
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	4 Main Memory
		4.1 Introduction
		4.2 Basics of Digital Circuits: A Quick Review
			4.2.1 MOS Transistor as a Switch
			4.2.2 CMOS Inverter
			4.2.3 Bistable Element
		4.3 SRAM Cell
		4.4 DRAM Cell
			4.4.1 Basic Operation of DRAM
			4.4.2 Basic Operation of Sense Amplifiers
		4.5 DRAM Arrays and DRAM Banks
		4.6 DRAM Chips
		4.7 Basic DRAM Operations and Timings
			4.7.1 Reading Data from DRAM Memory
			4.7.2 Writing Data to DRAM Memory
			4.7.3 Refreshing the DRAM Memory
		4.8 Improving the Performance of DRAMs
			4.8.1 Fast Page Mode DRAM
			4.8.2 Extended Data Output DRAM
		4.9 Synchronous DRAM
			4.9.1 Functional Description
			4.9.2 Basic Operations and Timings
			4.9.3 Case Study: Using the STM32F Flexible Memory Controller  to Access SDRAM
		4.10 Double Data Rate SDRAM
			4.10.1 Functional Description
			4.10.2 DDR SDRAM Timing Diagrams
			4.10.3 Address Mapping
			4.10.4 Memory Timings: A Summary
			4.10.5 DDR Versions
		4.11 DIMM Modules
			4.11.1 Micron DDR4 DIMM Module
		4.12 Memory Channels
			4.12.1 Case Study: Intel i7-860 Memory
			4.12.2 Case Study: i9-9900K Memory
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	5 Caches
		5.1 Introduction
		5.2 Memory Hierarchy
		5.3 Cache Structure and Organisation
		5.4 Direct Mapped Cache
			5.4.1 Read Operations in Direct-Mapped Caches
			5.4.2 Handling Writes in Direct-Mapped Caches
		5.5 Set Associative Cache
			5.5.1 Replacing a Block in a Set-Associative Cache
			5.5.2 Choosing the Associativity Level
		5.6 Cache Controller
		5.7 Case Study: Cache in STM32F7 and STM32H7 Series Devices
		5.8 Case Study: Cache in Processors with ARMv8-A Architecture
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	6 Virtual Memory
		6.1 Introduction
		6.2 The Benefits and Downsides of Virtual Memory
		6.3 Memory Management Unit
		6.4 Virtual Address Translation
		6.5 One-Level Paging
		6.6 Two-Level Paging
		6.7 Translation Lookaside Buffers
			6.7.1 Multilevel Translation Lookaside Buffers
		6.8 Integrating Caches and Virtual Memory
			6.8.1 Physically Indexed and Physically Tagged (PIPT) Cache
			6.8.2 Virtually Indexed and Virtually Tagged (VIVT) Cache
			6.8.3 Virtually Indexed and Physically Tagged (VIPT) Cache
		6.9 Case Study: AMD64 5-Level Paging
		6.10 Summary of Memory Hierarchy
		6.11 Case Study: The Memory Hierarchy in an Intel Core i7
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	Index