Trusted Execution Environments

Contents
Acronyms
List of Figures
List of Tables
Listings
Part I Foundations
	1 Introduction
		1.1 Why OS Security Is Not Enough
		1.2 Confidential Computing
		1.3 Scope
		1.4 Target Audience
		References
	2 Background Material
		2.1 Central Processing Unit Basics
		2.2 Memory Hierarchy
		2.3 Protection Rings
			2.3.1 X86-64
			2.3.2 ARM Exception Model
			2.3.3 RISC-V Privilege Modes
		2.4 Modern CPU Optimisations
			2.4.1 Pipelining
			2.4.2 Out-of-Order Execution
			2.4.3 Speculative Execution
		2.5 Virtual Memory Management
		2.6 Memory Protection
		2.7 Motherboards and Memory Controllers
		2.8 System-on-Chips
		References
Part II Technologies for Secure and Trusted Execution
	3 Operating System Controls
		3.1 Overview
		3.2 Users, Groups, and Permissions
		3.3 Sandboxing
			3.3.1 Linux System Calls and Secure Computing Mode
			3.3.2 OS-Level Virtualisation
				3.3.2.1 Chroot Jail
				3.3.2.2 Namespace Separation
				3.3.2.3 Control Groups (cgroups)
		3.4 Mandatory Access Control
			3.4.1 SELinux
			3.4.2 AppArmor
		3.5 Case Study: Linux Containers
		3.6 Discussion
		3.7 Using Hardware to Protect Software: The Case of Secure Boot
		References
	4 Isolated Hardware Execution Platforms
		4.1 Introduction
		4.2 Smart Cards
			4.2.1 Java Card
			4.2.2 Case Study: EMV Payment Transactions
				4.2.2.1 A Simplified Transaction
				4.2.2.2 Remarks
		4.3 Certifying a Security Platform
			4.3.1 Common Criteria
			4.3.2 The Federal Information Processing Standards
		4.4 Secure Elements
			4.4.1 GlobalPlatform Secure Element Specifications
			4.4.2 Host-Based Card Emulation
		4.5 Google Titan M
		4.6 Apple Secure Enclave
		References
	5 Building Execution Environments from the Trusted Platform Module
		5.1 Introduction
		5.2 Trusted Platform Module
			5.2.1 Measured Boot
			5.2.2 Remote Attestation
			5.2.3 Binding and Sealing for Secure Storage
			5.2.4 TCG TPM 1.2 and 2.0
			5.2.5 Additional TCG TPM Standards
			5.2.6 Dynamic Root of Trust
		5.3 Microsoft Palladium
		5.4 Intel Trusted Execution Technology
		5.5 AMD Secure Virtual Machine and Secure Encrypted Virtualisation
		5.6 Flicker
		5.7 TrustVisor
		References
	6 Trusted World Systems
		6.1 Introduction
		6.2 GlobalPlatform TEE
			6.2.1 System Architecture
				6.2.1.1 Initialisation
				6.2.1.2 TA Requirements and Organisation
			6.2.2 Client and Internal Core API Concepts
				6.2.2.1 TA Communication
				6.2.2.2 Secure Storage
				6.2.2.3 Cryptographic Operations
			6.2.3 Additional APIs
				6.2.3.1 Sockets API
				6.2.3.2 Trusted User Interface API
				6.2.3.3 Secure Element API
			6.2.4 Deployment Model
			6.2.5 Protection Profile
		6.3 ARM TrustZone
			6.3.1 TrustZone for Cortex-A
				6.3.1.1 TrustZone Protection Controller
				6.3.1.2 TrustZone Memory Adapter
				6.3.1.3 TrustZone Address Space Controller
				6.3.1.4 Protecting Cache Contents
				6.3.1.5 Protecting TLB Entries
				6.3.1.6 Secure Boot
				6.3.1.7 Interrupt Handling
			6.3.2 TrustZone for Cortex-M
		6.4 ARM Confidential Compute Architecture
		6.5 Case Study: Android Keystore
		6.6 Case Study: Android Fingerprint Authentication
		References
	7 Enclave Computing
		7.1 Introduction
		7.2 Intel Software Guard Extensions
			7.2.1 Software Architecture
			7.2.2 Memory Organisation
				7.2.2.1 Processor Reserved Memory
				7.2.2.2 Enclave Page Cache
			7.2.3 Intel Memory Encryption Engine
			7.2.4 Memory Access Control Enforcement
			7.2.5 Launch and Tear-down Procedures
			7.2.6 Attestation
				7.2.6.1 Local Attestation
				7.2.6.2 Remote Attestation
			7.2.7 Sealing
		7.3 Intel Trust Domain Extensions
			7.3.1 Trust Domain Lifecycle
				7.3.1.1 Context Switching Overview
				7.3.1.2 Creating Trust Domains
				7.3.1.3 Entering and Exiting Trust Domains
			7.3.2 Memory Protection and Encryption
			7.3.3 Physical Memory Organisation
			7.3.4 Remote Attestation
		7.4 Research Proposals
			7.4.1 Komodo
			7.4.2 Sanctum
			7.4.3 Keystone
		References
Part III Ongoing and Future Considerations
	8 Deployment Issues, Attacks, and Other Challenges
		8.1 Introduction
		8.2 Deployment Issues
			8.2.1 Closed-Source Technology Development
			8.2.2 Large and Dynamic TCBs
			8.2.3 Fragmentation
		8.3 Attacks
			8.3.1 Implementation Errors and Improper Usage
			8.3.2 Software Side-Channel Attacks
				8.3.2.1 Cache Attacks
				8.3.2.2 Transient Execution Attacks
			8.3.3 Physical Side-Channel Attacks
			8.3.4 Fault Injections
		8.4 Certification Shortcomings
		8.5 Ethical Considerations
			8.5.1 Privacy and Surveillance
			8.5.2 Curtailing User Freedom
		References
	9 Conclusion
		9.1 The Journey So Far
		9.2 Major Takeaways
			9.2.1 Lack of Universality
			9.2.2 Attacks and Vulnerabilities Against TEEs: A Pragmatic Perspective
			9.2.3 Considering TEEs in a Wider Security Context
		9.3 Final Thoughts: The Road Ahead
		References
Index