Transient-Induced Latchup in CMOS Integrated Circuits

Front Cover......Page 1
Front Matter......Page 2
Copyright Page......Page 5
Contents......Page 6
Preface......Page 12
1.1 Latchup Overview......Page 15
1.3 Categories of TLU-Triggering Modes......Page 21
1.4 TLU Standard Practice......Page 30
References......Page 33
2.1 Background......Page 37
2.2 TLU in the System-Level ESD Test......Page 38
2.3 Test Structure......Page 40
2.4 Measurement Setup......Page 42
2.5 Device Simulation......Page 44
2.6 TLU Measurement......Page 49
2.7 Discussion......Page 51
2.8 Conclusion......Page 53
References......Page 54
3.1 Background......Page 55
3.2 Component-Level TLU Measurement Setup......Page 56
3.3 Influence of the Current-Blocking Diode and Current-Limiting Resistance on the Bipolar Trigger Waveforms......Page 58
3.4 Influence of the Current-Blocking Diode and Current-Limiting Resistance on the TLU Level......Page 61
3.5 Verifications of Device Simulation......Page 64
3.6 Suggested Component-Level TLU Measurement Setup......Page 67
3.7 TLU Verification on Real Circuits......Page 68
3.8 Evaluation on Board-Level Noise Filters to Suppress TLU......Page 70
3.9 Conclusion......Page 74
References......Page 75
Nomenclature......Page 76
4.1 Examples of Different DFreq and DFactor in the System-Level ESD Test......Page 77
4.2 TLU Dependency on DFreq and DFactor......Page 80
4.3 Experimental Verification on TLU......Page 83
4.4 Suggested Guidelines for TLU Prevention......Page 85
4.5 Conclusion......Page 87
References......Page 88
5.1 Electrical Fast Transient Test......Page 89
5.2 Test Structure......Page 92
5.3 Experimental Measurements......Page 94
5.4 Evaluation on Board-Level Noise Filters to Suppress TLU in the EFT Test......Page 97
5.5 Conclusion......Page 101
References......Page 102
6.1 Introduction......Page 103
6.2 Latchup Test......Page 104
6.3 Extraction of Layout Rules for I/O Cells......Page 108
6.4 Extraction of Layout Rules for Internal Circuits......Page 113
6.5 Extraction of Layout Rules between I/O Cells and Internal Circuits......Page 118
6.6 Conclusion......Page 124
References......Page 125
7.1 Latchup between Two Different Power Domains......Page 127
7.2 Latchup in Internal Circuits Adjacent to Power-Rail ESD Clamp Circuits......Page 131
7.3 Unexpected Trigger Point to Initiate Latchup in Internal Circuits......Page 133
7.4 Other Unexpected Latchup Paths in CMOS ICs......Page 137
7.5 Conclusion......Page 139
References......Page 140
8.1 In LV CMOS ICs......Page 142
8.2 In HV CMOS ICs......Page 153
8.3 Conclusion......Page 161
References......Page 162
9.1 TLU in CMOS ICs......Page 164
9.2 Extraction of Compact and Safe Layout Rules for Latchup Prevention......Page 166
A.1 For I/O Cells......Page 167
A.2 For Internal Circuits......Page 174
A.3 For between I/O and Internal Circuits......Page 177
A.4 For Circuits across Two Different Power Domains......Page 182
A.5 Suggested Layout Guidelines......Page 185
Index......Page 188