The Designer's Guide to the Cortex-M Processor Family: A Tutorial Approach

Front Cover
The Designer’s Guide to the Cortex-M Processor Family
Copyright Page
Contents
About the author
Foreword
Preface
Acknowledgments
1 Introduction to the Cortex-M Processor Family
	Introduction
	Book Structure
		External URL
	Cortex-M Processor Family
		Cortex Profiles
		Cortex-M Hardware Architectures
	Armv7-M
		Cortex-M3
		Cortex-M4
		Cortex-M7
	Armv6-M
		Cortex-M0
		Cortex-M0+
	Armv8-M
		Cortex-M33/M23
	Armv8.1-M
		Cortex-M55
		Cortex-M85
	Conclusion
2 Developing Software for the Cortex-M Family
	Introduction
	Keil Microcontroller Development Kit
		Community Edition
		Software Packs
	The Tutorial Exercises
	Installation
	Exercise 2.1: Building a First Program
		The Blinky Project
		Configuring a Project from Scratch
		Configuring the Run Time Environment
		Project Configuration
	Exercise 2.2: Hardware Debug
		How to Get Out of Jail Free
		Startup Barrier
	Third-Party Configuration Tools
	Conclusion
3 Cortex-M Architecture
	Introduction
	Cortex-M Instruction Set
	Programmer’s Model and CPU Registers
		Program Status Register
		Q Bit and Saturated Math’s Instructions
		Interrupts and Multicycle Instructions
		Conditional Execution—If Then blocks
		Exercise 3.1: Saturated Maths and Conditional Execution
	Cortex-M Memory Map and Busses
		Write Buffer
		Memory Barrier Instructions
		System Control Block
		Memory Access
	Bit Manipulation
		Exercise 3.2: Bit Banding
		Dedicated Bit Manipulation Instructions
	SysTick Timer
	Nested Vector Interrupt Controller
		Operating Modes
		Interrupt Handling—Entry
		Interrupt Handling—Exit
		Exiting Interrupt Routines Important!
		Exercise 3.3: SysTick Interrupt
		Cortex-M Processor Exceptions
		Usage Fault
		Bus Fault
		Memory Manager Fault
		Hard Fault
		Enabling Fault Exceptions
		Priority and Preemption
		Groups and Subgroup
		Processor Exceptions
		Run Time Priority Control
		Exception Model
		NVIC Tail Chaining
		NVIC Late Arriving
		NVIC POP Preemption
		Exercise 3.4: Working with Multiple Interrupts
		Bootloader Support
		Exercise 3.5: Bootloader
	Power Management
		Entering Low-Power Modes
		Configuring the Low-Power Modes
		Exercise 3.6: Low-Power Modes
	Moving From the Cortex-M3
		Cortex-M4
		Cortex-M0
		Cortex-M0+
	Conclusion
4 Common Microcontroller Software Interface Standard
	Introduction
	CMSIS Specifications
		CMSIS-Core
		CMSIS-RTOS
		CMSIS-DSP
		CMSIS-Driver
		CMSIS-SVD and DAP
		CMSIS-Pack
		CMSIS-NN
		CMSIS-ZONE
		CMSIS-Build
	Overview of CMSIS-Core
		Coding Rules
			MISRA-C
		CMSIS-Core Structure
			Startup code
			System Code
			Device Header File
			CMSIS-Core Header files
		Interrupts and Exceptions
		Exercise 4.1: CMSIS and User Code Comparison
		CMSIS-Core Register Access
		CMSIS-Core CPU Intrinsic Instructions
		Exercise 4.2: Intrinsic Bit Manipulation
		CMSIS SIMD Intrinsics
		CMSIS-Core Debug Functions
			Hardware Breakpoint
			Instrumentation Trace
		CMSIS Core Functions for Corex-M7
			MPU Support
		Armv8-M Support
	Conclusion
5 Advanced Architecture Features
	Introduction
	Cortex Processor Operating Modes
		Exercise 5.1: Stack Configuration
		Supervisor Call
		Exercise 5.2: SVC
		PEND_SV Exception
		Exercise 5.3: Pend_SV
	Interprocessor Events
		Exclusive Access Instructions
		Exercise 5.4: Exclusive Access
	Memory Protection Unit
		Configuring the MPU
		CMSIS Core MPU Support
		Exercise 5.5: MPU Configuration
		Memory Protection Unit Subregions
		Memory Protection Unit Limitations
		AHB Lite Bus Interface
	Conclusion
6 Cortex-M7 Processor
	Introduction
	Superscaler Architecture
	Branch Prediction
		Exercise 6.1: Simple Loop
	Bus Structure
	Memory Hierarchy
		Exercise 6.2: Locating Code and Data into the TCM
	Open Main.c
		Cache Units
		Cache Operation
		Instruction Cache
		Exercise 6.3: Instruction Cache
	Data Cache
		Memory Barriers
		Example 6.4: Data Cache
		MPU and Cache Configuration
		Cache Policy
			Managing the Data Cache
			Switch off the Cache
			Disable Caching Over a Region of System Memory
			Change the Cache Policy for a Region of System Memory
			Use the Cache Management Functions to Guarantee Coherency
			Exercise 6.5: Data Cache Configuration
	Double Precision Floating Point Unit
	Functional Safety
		Cortex-M7 Safety Features
		Safety Documentation
	Conclusion
7 Armv8-M Architecture and Processors
	Introduction
	Armv8-M
		Common Architectural Enhancements
		Armv8 Baseline Enhancements
		Armv8-M Mainline Enhancements
		Coprocessor Interface
		Trust Zone
			Interrupts and Exceptions
			CMSIS Trust Zone Support
			Platform Security Architecture
		Exercise 7.1: TrustZone Configuration
	Armv8.1-M
		Helium Vector Extension
			FPU Register Organization
			Lane Prediction
			Big Integer Support
			Data Load and Store Instructions
				Vector Load and Store
				Data Interleaving and Deinterleaving
				Scatter Load and Unload
			Helium Data Throughput
			Developing Applications with Helium
				CMSIS-Enabled Helium Libraries
				Helium Code Development
				Auto Vectorizing Compiler
		CPU Extension
			Low Overhead Branch Extension
		Exercise 7.2: Armv8.1 Performance
		Coresight Debug Enhancements
		Memory Error Correction Codes
			Poison Signaling
			Reliability Availability and Serviceability
				Error Synchronization Barrier
				RAS Error Event
		Performance Monitoring
		Security
			Pointer Authentication and Branch Target Identification Extension
				Pointer Authentication
			Branch Target Identification
			PACBTI Compiler Support
			TrustZone Support
			Unprivileged Debug Extension
	CPU Comparison
	Conclusion
8 Debugging With CoreSight
	Introduction
	CoreSight Hardware
	Debugger Hardware
	CoreSight Debug Architecture
		Debug Adapters
		Exercise 8.1: CoreSight Debug
			Hardware Configuration
			Software Configuration
		Debug Limitations
	Customizing the Debugger
		Instrumentation Trace
		Exercise 8.2: Setting up the ITM
		Event Recorder
		Exercise 8.3: Basic Event Recorder
		Event Recorder Annotations
		Exercise 8.4: Event Viewer Annotations
		Exercise 8.5: Customizing the Debugger I
		Component Viewer
		Exercise 8.6: Customizing the Debugger II
	System Control Block Debug Support
		Tracking Faults
		Exercise 8.7: Processor Fault Exceptions
	Power Analysis
	Instruction Trace With the Embedded Trace Macro Cell
		Exercise 8.8: Using the ETM Trace
	CMSIS-DAP
	Cortex-M0+ Micro Trace Buffer
		Exercise 8.9: Micro Trace Buffer
	System Viewer
	Conclusion
9 Practical DSP for Cortex-M Microcontrollers
	Introduction
	Hardware Floating Point Unit
		FPU Integration
		FPU Registers
		Cortex-M7 FPU
		Enabling the FPU
		Exceptions and the FPU
		Using the FPU
		Exercise 9.1: Floating Point Unit
	Cortex-M4/M7 DSP and SIMD Instructions
		Exercise 9.2: SIMD Instructions
		Exercise 9.3: Optimizing DSP Algorithms
	The CMSIS-DSP Library
		CMSIS-DSP Library Functions
		Exercise 9.4: Using the CMSIS-DSP Library
	DSP Data Processing Techniques
		Exercise 9.5: FIR Filter with Block Processing
		Fixed Point DSP with Q Numbers
		Exercise 9.6: Fixed Point FFT Transform
	Machine Learning
		Classical Machine Learning
			Support Vector Machine
			Naive Gaussian Bayes Estimator
			Mel Frequency Cepstral Transform
		CMSIS-Neural Net
		Micro Neural processing Unit
	Conclusion
10 Using a Real-Time Operating System
	Introduction
		First Steps With CMSIS-RTOS2
	Accessing the CMSIS-RTOS2 API
	Threads
		Understanding the Scheduler
		Starting the RTOS
			Exercise 10.1: A First CMSIS-RTOS2 Project
		Advanced Debug Features
			Exercise 10.1: Continued—RTOS Debugger Support
		Creating Threads
			Exercise 10.2: Creating and Managing Threads
		Thread Management and Priority
			Exercise 10.2: Continued—Creating and Managing Threads
		Memory Management
			Exercise 10.3: Memory Model
		Joinable Threads
			Exercise 10.4: Joinable Threads
		Multiple Instances
			Exercise 10.5: Multiple Thread Instances
	Understanding RTOS API Calls
	Time Management
		Time Delay
		Absolute Time Delay
			Exercise 10.6: Time Management
		Virtual Timers
			Exercise 10.7: Virtual Timer
		Idle Thread
			Exercise 10.8 Idle Thread
		Performance Analysis During Hardware Debugging
	Inter-Thread Communication
		Thread Flags
			Exercise 10.9: Thread Flags
		Event Flags
			Exercise 10.10: Event Flags
		Semaphores
			Exercise 10.11 Semaphore Signaling
			Using Semaphores
			Signaling
			Multiplex
				Exercise 10.12: Multiplex
			Rendezvous
				Exercise 10.13: Rendezvous
			Barrier Turnstile
				Exercise 10.14: Semaphore Barrier
			Semaphore Caveats
		Mutex
			Exercise 10.15: Mutex
			Mutex Caveats
	Data Exchange
		Message Queue
			Exercise 10.16: Message Queue
		Extended Message Queue
			Exercise 10.17: Message Queue
		Message Queue API
		Memory Pool
			Exercise 10.18: Zero Copy Mailbox
	Configuration
		System Configuration
		Thread Configuration
		System Timer Configuration
	RTX5 License
	Conclusion
11 RTOS Techniques
	Introduction
	RTOS and Interrupts
	RTOS Interrupt Handling
		Exercise 11.1: RTOS Interrupt Handling
	User Supervisor Functions
	Exercise 11.2: RTOS and User SVC Exceptions
	Power Management
		Power Management First Steps
		Power Management Strategy
	Watchdog Management
		Integrating Interrupt Service Routines
		Exercise 11.3: Power and Watchdog Management
		Startup Barrier
	Designing for Real Time
		Buffering Techniques – The Double or Circular Buffer
		Buffering Techniques FIFO Memory Pool
		Exercise 11.4: RTX Real Time
	Functional Safety
	Arm Functional Safety Run-Time System
		Software Test Library
		RTX Safety Features
		FuSa RTX Kernel
			Spatial Isolation
		MPU Protection Zones
			Defining the Memory Map
			Placing the Resources
			Configuring the MPU
			Memory Protection Zone RTOS Functions
			CMSIS Zone Utility
		Safety Class
			Safety Class Management
		Temporal Isolation
		Fault Handling
			Safe Mode Operation Thread
		Additional Safety Features
			Object Pointer Checking
			Accessing Privileged Resources
			SVC Pointer Checking
	Conclusion
12 CMSIS-Driver
	Introduction
	CMSIS-Driver API
		Exercise 12.1: CMSIS-Driver
	Driver Validation
		Exercise 12.2: Driver Validation
	CMSIS Virtual IO
		CMSIS VIO API Functions
			Exercise 12.3: CMSIS-VIO
		Implementing the VIO Driver
	Extending the CMSIS-Driver Specification
		Custom CMSIS-Driver
			Exercise 12.4: CMSIS Timer
		Custom Driver Validation
		Exercise 12.5: Custom Driver Validation
	Conclusion
13 Test-Driven Development
	Introduction
	The TDD Development Cycle
		Test Framework
		Test Framework Integration
		Test Framework Automation
	Designing for Testability
		Software Testing with Sub-Projects
	Exercise 13.1: Test-Driven Development
		Adding the Unity Test Framework
		Adding the Test Cases
		Automating the TDD Cycle
	Testing RTOS Treads
	Exercise 13.2: Testing RTOS Threads
		Decoupling Low-Level Functions
	Testing Interrupts
	Exercise 13.3: Testing with Interrupts
	Conclusion
14 Software Components
	Introduction
	Designing a Software Component
		Component API
		Module Structure
		Development Workflow
		Exercise 14.1 Component GPS Interface
	Adding Custom IDE Support
		Configuration Wizard
		Component Viewer
		Event Recorder
			Event Recorder Message ID Format
		Component Characterization
		Exercise 14.2 GPS Component
		Designing a Configuration Wizard
		Exercise Configuration Wizard
	Software Component Reuse with CMSIS Pack
		CMSIS Pack Structure
		CMSIS Pack Utilities
		Updating and Testing the Software Component
		Generating the Component Pack
		Autogenerated Header Files
		Adding Example Projects
		Deploying Software Components
	Conclusion
15 MCU Software Architecture
	Introduction
	Software Architecture for Microcontrollers
		Superloop
		Time-Triggered Architecture
		Event-Triggered Architecture
		RTOS
		Objectives of our Architecture
			Requirements Capture
			Modular Design
			Code Reuse
			Testing
			Early Software Development
			Improved Workflow
			Maintenance and Extension
			Portability
			Increased Productivity and Quality
		RTOS-Layered Architecture
			Bootloader
			Firmware Driver Layer
			Service Layer
			RTOS Layer
			Application Layer
				Supervisor Thread
				System Header File
		Design Synthesis
		Implementation
			Designing the Application Layer
			Assigning Thread Priorities
			Will it Schedule?
				Utilization Bound Theorem
				Completion Time Theorem
				Asynchronous Threads
			Scheduling a Real-Time System
				Preemption Utilization
				Blocking Time
			Component Characterization
		Additional Tools
			Coding Standard
			Static Checker
			Metrics
			Documentation Generator
		Exercise 15.1: Case Study
	Continuous Integration
		Exercise 15.2: Cloud-Based Continuous Integration
	CMSIS-Toolbox
		CMSIS-Toolbox Project Format
		Layers
		Exercise 15.3: Configuring CMSIS-Toolbox
16 The Road Ahead
	Keil Studio
		Arm Virtual Hardware
			Streaming Interfaces
	IoT and Machine Learning
		Project Centauri for the IoT
		CMSIS v6
			CMSIS-Classic
			Open-CMSIS-CDI
				Arm-2D
			Open-CMSIS-Pack
	Machine Learning
		Confidential AI
	Conclusion
Appendix A
	Chapter 1
		Accompanying videos and webinars
		Keil device database
		Cortex-M Wikipedia page
		PSA certified
		Training companies
	Chapter 2
		Books
		Keil website resources
		STM32 Cube MX Download
		Cortex-M development tools
		Online development tools
	Chapter 3
		Books
			The Definitive Guide to the Cortex-M3, Joseph Yui
			Insiders Guide to the STM32
			Arm documentation
			Architecture reference manual
			Technical reference manual
	Chapter 4
		CMSIS online specification
		CMSIS Github repository
		MISRA-C
	Chapter 5
		Armv7 Memory protection unit
		Changes for the Armv8 Memory protection Unit
		CMSIS Core MPU support
	Chapter 6
		Technical reference manual
	Chapter 7
		Architecture reference manual
		Technical reference manuals
	Chapter 8
		Microvision debugger manual
		Ulink debug adapters
		Ulink support notes
	Chapter 9
		Books
		Technical Reference Manual
		Tools
	Chapter 10
		Books
		RTOS
	Chapter 11
		CMSIS Zone specification
		CMSIS Zone utility repository
		Functional Safety
	Chapter 12
		CMSIS Driver specification
		Driver template repository
		Driver validation repository
	Chapter 13
		Books
		Test Frameworks
		Unit test tools
	Chapter 14
		Open-CMSIS-Pack
		CMSIS-Pack specification
	Chapter 15
		Books
		Tools
		CMSIS-Toolbox
		CMSIS-Toolbox specification
		CMSIS-Toolbox repository
	Chapter 16
Index
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