The Definitive Guide to the ARM Cortex-M3

Cover\r......Page 1
Copyright page......Page 2
Foreword......Page 3
Foreword......Page 4
Acknowledgments......Page 5
Conventions......Page 6
Terms and Abbreviations......Page 7
What Is the ARM Cortex-M3 Processor?......Page 9
A Brief History......Page 10
Architecture Versions......Page 11
Processor Naming......Page 13
Instruction Set Development......Page 15
The Thumb-2 Technology and Instruction Set Architecture......Page 16
Cortex-M3 Processor Applications......Page 17
Further Reading......Page 18
Fundamentals......Page 19
R13: Stack Pointers......Page 20
Special Registers......Page 21
Operation Modes......Page 22
Nested Interrupt Support......Page 23
The Memory Map......Page 24
The Bus Interface......Page 25
The Instruction Set......Page 26
Interrupts and Exceptions......Page 27
Low Power and High Energy Efficiency......Page 28
Debugging Support......Page 29
Advanced Interrupt-Handling Features......Page 30
Debug Supports......Page 31
General Purpose Registers R8 through R12......Page 33
Stack Pointer R13......Page 34
Program Counter R15......Page 36
Program Status Registers......Page 37
PRIMASK, FAULTMASK, and BASEPRI Registers......Page 38
The Control Register......Page 39
Operation Mode......Page 40
Exceptions and Interrupts......Page 43
Stack Memory Operations......Page 44
Cortex-M3 Stack Implementation......Page 45
The Two-Stack Model in the Cortex-M3......Page 47
Reset Sequence......Page 48
Assembler Language: Basic Syntax......Page 51
Assembler Language: Use of Suffixes......Page 52
Assembler Language: Unified Assembler Language......Page 53
Instruction List......Page 54
Unsupported Instructions......Page 59
Instruction Descriptions......Page 60
Assembler Language: Moving Data......Page 61
LDR and ADR Pseudo-Instructions......Page 64
Assembler Language: Processing Data......Page 65
Assembler Language: Call and Unconditional Branch......Page 68
Assembler Language: Decisions and Conditional Branches......Page 70
Assembler Language: Combined Compare and Conditional Branch......Page 73
Assembler Language: Instruction Barrier and Memory Barrier Instructions......Page 75
Assembly Language: Saturation Operations......Page 76
More on the IF-THEN Instruction Block......Page 78
SDIV and UDIV......Page 80
SXTB, SXTH, UXTB, and UXTH......Page 81
LDRD and STRD......Page 82
Table Branch Byte and Table Branch Halfword......Page 83
Memory Maps......Page 86
Memory Access Attributes......Page 89
Default Memory Access Permissions......Page 90
Bit-Band Operations......Page 91
Advantages of Bit-Band Operations......Page 94
Bit-Band Operations in C Programs......Page 97
Unaligned Transfers......Page 99
Exclusive Accesses......Page 100
Endian Mode......Page 102
The Pipeline......Page 105
A Detailed Block Diagram......Page 107
The External PPB......Page 110
The External PPB......Page 111
Typical Connections......Page 112
Reset Types and Reset Signals......Page 113
Exception Types......Page 115
Definitions of Priority......Page 117
Vector Tables......Page 123
Interrupt Inputs and Pending Behavior......Page 124
Fault Exceptions......Page 126
Bus Faults......Page 127
Memory Management Faults......Page 128
Usage Faults......Page 129
Dealing with Faults......Page 131
Supervisor Call and Pendable Service Call......Page 132
Nested Vectored Interrupt Controller Overview......Page 136
Priority Levels......Page 137
Active Status......Page 139
PRIMASK and FAULTMASK Special Registers......Page 140
The BASEPRI Special Register......Page 141
Configuration Registers for Other Exceptions......Page 142
Example Procedures In Setting Up an Interrupt......Page 143
Software Interrupts......Page 145
The SYSTICK Timer......Page 146
Stacking......Page 149
Exception Exits......Page 151
Tail-Chaining Interrupts......Page 152
More on the Exception Return Value......Page 153
Stacking......Page 156
Invalid Returns......Page 157
A Typical Development Flow......Page 158
Using C......Page 159
Example of a Simple C Program Using RealView Development Site......Page 160
Compile the Same Example Using Keil MDK-ARM......Page 162
Accessing Memory-Mapped Registers in C......Page 164
Embedded Assembler and Inline Assembler......Page 166
Background of CMSIS......Page 167
Areas of Standardization......Page 168
Organization of CMSIS......Page 169
Using CMSIS......Page 170
Benefits of CMSIS......Page 171
Using Assembly......Page 172
The First Step in Assembly Programming......Page 173
Producing Outputs......Page 174
The “Hello World” Example......Page 175
Using Data Memory......Page 179
Using Exclusive Access for Semaphores......Page 180
Using Bit Band for Semaphores......Page 182
Working with Bit Field Extract and Table Branch......Page 184
Stack Setup......Page 185
Vector Table Setup......Page 186
Interrupt Priority Setup......Page 187
Enable the Interrupt......Page 188
Exception/Interrupt Handlers......Page 190
Software Interrupts......Page 191
Example of Vector Table Relocation......Page 192
Using SVC......Page 195
SVC Example: Use for Text Message Output Functions......Page 196
Using SVC with C......Page 199
Running a System with Two Separate Stacks......Page 202
Double-Word Stack Alignment......Page 205
Nonbase Thread Enable......Page 206
Performance Considerations......Page 207
What Happens During Lockup?......Page 209
FAULTMASK......Page 211
Overview......Page 212
MPU Registers......Page 213
Setting Up the MPU......Page 219
Example Use of the Subregion Disable......Page 226
The SYSTICK Timer......Page 230
Sleep Modes......Page 233
Wakeup Interrupt Controller......Page 235
Multiprocessor Communication......Page 237
Self-Reset Control......Page 242
Debugging Features Overview......Page 244
The Debug Host Interface......Page 245
DP Module, AP Module, and DAP......Page 246
CoreSight Characteristics......Page 247
Debug Modes......Page 249
Debugging Events......Page 251
Breakpoint in the Cortex-M3......Page 252
Accessing Register Content in Debug......Page 254
Other Core Debugging Features......Page 255
The Trace System in the Cortex-M3......Page 256
Trace Components: DWT......Page 257
 Trace Components: ITM......Page 259
Software Trace with the ITM......Page 260
Trace Components: ETM......Page 261
Trace Components: TPIU......Page 262
Flash Patch Feature......Page 263
Comparators......Page 264
The Advanced High-Performance Bus Access Port......Page 265
ROM Table......Page 266
Choosing a Cortex-M3 Product......Page 269
Development Tools......Page 270
C Compiler and Debuggers......Page 271
Differences between the Cortex-M3 Revision 0 and Revision 1......Page 272
Differences between the Cortex-M3 Revision 1 and Revision 2......Page 274
Debug Features......Page 275
Sleep Features......Page 276
Benefits and Effects of the Revision 2 New Features......Page 277
Programmer’s Model......Page 278
Instruction Set......Page 279
Compatibility......Page 280
System Characteristics......Page 282
Interrupts......Page 283
Operation Modes......Page 284
ARM State......Page 285
Precompiled Object Files......Page 287
Optimization......Page 288
Background......Page 289
Development Flow......Page 290
Example 1: The First Program......Page 292
Example 2: Linking Multiple Files......Page 294
Example 3: A Simple “Hello World” Program......Page 295
Example 4: Data in RAM......Page 297
Example 5: C Program......Page 298
Example 6: C with Retargeting......Page 300
Accessing Special Registers......Page 302
Inline Assembler in the GNU C Compiler......Page 303
Overview......Page 304
Getting Started with ?Vision......Page 305
Outputting the “Hello World” Message Via Universal Asynchronous Receiver/Transmitter......Page 311
Testing the Software......Page 314
Using the Debugger......Page 315
The Instruction Set Simulator......Page 322
Modifying the Vector Table......Page 323
Stopwatch Example with Interrupts with CMSIS......Page 324
Porting Existing Applications to Use CMSIS......Page 331
What Is LabVIEW......Page 332
Development Flow......Page 334
Create the Project......Page 336
Create the Program......Page 338
Build the Design and Test the Application......Page 339
How It Works......Page 340
Additional Features in LabVIEW......Page 341
Porting to Another ARM Processor......Page 342
Instruction Set Summary......Page 345
Flexible Second Operand......Page 349
Shift Operations......Page 350
Address Alignment......Page 353
Conditional Execution......Page 354
Instruction Width Selection......Page 356
Memory Access InstructIons......Page 357
LDR and STR, Immediate Offset......Page 358
LDR and STR, Register Offset......Page 361
LDR and STR, Unprivileged......Page 362
LDR, PC-Relative......Page 363
LDM and STM......Page 364
PUSH and POP......Page 366
LDREX and STREX......Page 367
CLREX......Page 368
General Data-Processing Instructions......Page 369
ADD, ADC, SUB, SBC, and RSB......Page 370
AND, ORR, EOR, BIC, and ORN......Page 372
ASR, LSL, LSR, ROR, and RRX......Page 373
CMP and CMN......Page 374
MOV and MVN......Page 375
REV, REV16, REVSH, and RBIT......Page 377
TST and TEQ......Page 378
MUL, MLA, and MLS......Page 379
UMULL, UMLAL, SMULL, and SMLAL......Page 381
SSAT and USAT......Page 382
BFC and BFI......Page 384
SBFX and UBFX......Page 385
SXT and UXT......Page 386
B, BL, BX, and BLX......Page 387
IT......Page 389
TBB and TBH......Page 391
BKPT......Page 393
DMB......Page 394
ISB......Page 395
MSR......Page 396
NOP......Page 397
SVC......Page 398
WFI......Page 399
Appendix B The 16-Bit Thumb Instructions and Architecture Versions......Page 400
Exception Types and Enables......Page 401
Stack Contents After Exception Stacking......Page 402
Appendix D Nested Vectored Interrupt Controller and System Control Block Registers Quick Reference......Page 403
Overview......Page 415
Developing Fault Handlers......Page 416
Report Stacked PC and Other Stacked Registers......Page 417
Read Fault Address Register......Page 419
Understanding the Cause of the Fault......Page 420
Other Possible Problems......Page 423
Example Linker Script for Cortex-M3......Page 426
Exception and Interrupt Numbers......Page 431
NVIC Access Functions......Page 432
Core Registers Access Functions......Page 435
CMSIS Intrinsic Functions......Page 436
Debug Message Output Function......Page 437
The 20-Pin Cortex Debug + ETM Connector......Page 438
Legacy 38-Pin Mictor Connector......Page 440
References......Page 442
C......Page 443
H......Page 444
P......Page 445
U......Page 446
X......Page 447