Secured Hardware Accelerators for DSP and Image Processing Applications

Contents
Preface
Acknowledgements
About the author
List of acronyms
List of notations
1. Introduction: secured and optimized hardware accelerators for DSP and image processing applications | Anirban Sengupta
	1.1 Hardware accelerators: an introduction, definition, significance and applications
	1.2 Role of ESL synthesis in hardware accelerator design
	1.3 Hardware accelerators for popular DSP and image processing applications
	1.4 Security techniques/algorithms/modules for securing hardware accelerators
	1.5 A new paradigm in future ahead for EDA/VLSI/CE communities
	1.6 Conclusion
	1.7 Questions and exercise
	References
2. Cryptography-driven IP steganography for DSP hardware accelerators | Anirban Sengupta
	2.1 Introduction
	2.2 Contemporary approaches for securing hardware accelerators
	2.3 Crypto-based steganography for securing hardware accelerators
	2.4 Crypto-stego tool for securing hardware accelerators
	2.5 Case studies on DSP hardware accelerator applications
	2.6 Conclusion
	2.7 Questions and exercise
	References
3. Double line of defence to secure JPEG codec hardware for medical imaging systems | Anirban Sengupta
	3.1 Introduction
	3.2 Why secure JPEG codec processors used in medical imaging systems?
	3.3 Salient features of the chapter
	3.4 Securing JPEG compression hardware using a double line of defence
	3.5 Process of securing JPEG compression processor using double line of defence
	3.6 Analysis on case studies
	3.7 Conclusion
	3.8 Questions and exercise
	References
4. Integrating multi-key-based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators | Anirban Sengupta
	4.1 Introduction
	4.2 Salient features of the chapter
	4.3 Some practical applications of DSP hardware accelerators for modern electronic systems
	4.4 Overview of contemporary approaches
	4.5 Double line of defence using structural obfuscation and physical-level watermarking
	4.6 Low-cost optimized multi-key-based structural obfuscation
	4.7 Structural obfuscation and physical-level watermarking tool for securing hardware accelerators
	4.8 Analysis of case studies
	4.9 Conclusion
	4.10 Questions and exercise
	References
5. Multimodal hardware accelerators for image processing filters | Anirban Sengupta
	5.1 Introduction – why dedicated image processing filter hardware is needed?
	5.2 Why secure image processing filter hardware accelerators?
	5.3 Salient features of the chapter
	5.4 Selected contemporary approaches
	5.5 Theory of 3 x 3 filter hardware accelerator
	5.6 Designing functionally reconfigurable obfuscated (secured) 3 x 3 filter hardware accelerator
	5.7 Theory of 5 x 5 filter hardware accelerator
	5.8 Designing obfuscated (secured) 5 x 5 filter hardware accelerator
	5.9 Designing secured application specific filter hardware accelerators
	5.10 Equivalent MATLAB codes for image processing filters
	5.11 Additional information on image processing convolution filters
	5.12 Analysis of case studies
	5.13 Conclusion
	5.14 Questions and exercise
	References
6. Fingerprint biometric for securing hardware accelerators | Anirban Sengupta
	6.1 Introduction
	6.2 Salient features of the chapter
	6.3 Discussion on contemporary approaches
	6.4 Threat model
	6.5 High-level perspective of biometric fingerprinting approach for securing hardware accelerators
	6.6 Details of biometric fingerprinting approach for securing hardware accelerators
	6.7 Analysis on case studies
	6.8 Benefits and advantages of biometric-fingerprint-based IP protection
	6.9 Conclusion
	6.10 Questions and exercise
	References
7. Key-triggered hash-chaining-based encoded hardware steganography for securing DSP hardware accelerators | Anirban Sengupta
	7.1 Introduction
	7.2 Discussion on selected approaches
	7.3 Encoding and key-driven hash-chaining-based hardware steganography methodology
	7.4 Design process of securing FIR filter using encoding and key-driven hash-chaining steganography
	7.5 Key-triggered hash-chaining-driven steganography tool for securing hardware accelerators
	7.6 Analysis on case studies
	7.7 Conclusion
	7.8 Questions and exercise
	References
8. Designing a secured N-point DFT hardware accelerator using obfuscation and steganography | Anirban Sengupta and Mahendra Rathor
	8.1 Introduction
	8.2 Secured N-point DFT hardware accelerator design methodology
	8.3 Analysis of case study
	8.4 Conclusion
	8.5 Questions and exercise
	References
9. Structural transformation-based obfuscation using pseudo-operation mixing for securing data-intensive IP cores | Anirban Sengupta and Mahendra Rathor
	9.1 Introduction
	9.2 Structural transformation-based obfuscation methodology
	9.3 Pseudo-operations mixing-based structural obfuscation tool
	9.4 Analysis on case studies
	9.5 Conclusion
	9.6 Questions and exercise
	References
Index