Reconfigurable Computing: Architectures, Tools and Applications: 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings

Front Matter....Pages -
FPGA Design Productivity – A Discussion of the State of the Art and a Research Agenda....Pages 1-1
Resiliency in Elemental Computing....Pages 2-2
The Colour of Embedded Computation....Pages 3-3
A HyperTransport 3 Physical Layer Interface for FPGAs....Pages 4-14
Parametric Design for Reconfigurable Software-Defined Radio....Pages 15-26
Hardware/Software FPGA Architecture for Robotics Applications....Pages 27-38
Reconfigurable Operator Based Multimedia Embedded Processor....Pages 39-49
A Protocol for Secure Remote Updates of FPGA Configurations....Pages 50-61
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing....Pages 62-73
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications....Pages 74-84
Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs....Pages 85-96
A Novel Local Interconnect Architecture for Variable Grain Logic Cell....Pages 97-109
Dynamically Adapted Low Power ASIPs....Pages 110-122
Fast Optical Reconfiguration of a Nine-Context DORGA....Pages 123-132
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep....Pages 133-144
On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks....Pages 145-156
A New Datapath Merging Method for Reconfigurable System....Pages 157-168
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform....Pages 169-180
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm....Pages 181-192
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs....Pages 193-203
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures....Pages 204-215
Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems....Pages 216-230
Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator....Pages 231-242
FPGA-Based Anomalous Trajectory Detection Using SOFM....Pages 243-254
SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems....Pages 255-260
A Parallel Branching Program Machine for Emulation of Sequential Circuits....Pages 261-267
Memory Sharing Approach for TMR Softcore Processor....Pages 268-274
The Need for Reconfigurable Routers in Networks-on-Chip....Pages 275-280
Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware....Pages 281-286
Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder....Pages 287-292
Tile-Based Fault Tolerant Approach Using Partial Reconfiguration....Pages 293-299
Regular Expression Pattern Matching Supporting Constrained Repetitions....Pages 300-305
Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function....Pages 306-311
AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications....Pages 312-317
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers....Pages 318-323
Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System....Pages 324-329
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture....Pages 330-335
A Hardware Accelerated Simulation Environment for Spiking Neural Networks....Pages 336-341
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia....Pages 342-348
Real Time Simulation in Floating Point Precision Using FPGA Computing....Pages 349-354
A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem....Pages 355-361
A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems....Pages 362-367
Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator....Pages 368-373
ACCFS – Operating System Integration of Computational Accelerators Using a VFS Approach....Pages 374-379
A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms....Pages 380-385
Back Matter....Pages -