Quantum-Dot Cellular Automata Circuits for Nanocomputing Applications

Cover
Half Title
Series Information
Title Page
Copyright Page
Table of Contents
Acknowledgement
Editors Bio
List of Contributors
1 Towards the Evaluation From Low Power VLSI to Quantum Circuits
	1.1 Introduction
	1.2 Need of Low Power Design
	1.3 Power Consumption in CMOS
		1.3.1 Dynamic Power
		1.3.2 Leakage / Static Power
		1.3.3 Short Circuit Power
	1.4 Different Levels of Abstraction of Customization
		1.4.1 System Level
		1.4.2 Algorithm Level
		1.4.3 Architecture Level
		1.4.4 Gate Level
		1.4.5 Transistor Level
	1.5 Power Optimization Methods
		1.5.1 Dynamic Power Reduction Methods
			1.5.1.1 Clock Gating
			1.5.1.2 Dual VDD
			1.5.1.3 Clustered Voltage Scaling (CVS)
			1.5.1.4 Multi-Voltage (MV)
			1.5.1.5 Dynamic Voltage and Frequency Scaling (DVFS)
			1.5.1.6 Adaptive Voltage Scaling (AVS)
		1.5.2 Static Power Reduction Methods
			1.5.2.1 Multi Threshold CMOS Optimization (MTCMOS)
			1.5.2.2 Transistor Stacking
			1.5.2.3 Sleepy Stack Approach
	1.6 Advanced Power Optimization Techniques
		1.6.1 Adiabatic Switching
			1.6.1.1 Partially Adiabatic Logic
			1.6.1.2 Fully Adiabatic Logic
		1.6.2 Quantum-Dot Cellular Automata
			1.6.3 Reversible Logic
	1.7 Comparison Between Some Power Reduction Techniques
	1.8 Summary of the Chapter
	References
2 Investigations On Designing of Adders, Multiplexers and Flip-Flops for Fast Memories Development in QCA Technology
	2.1 Introduction
	2.2 Quantum-Dot Cellular Automata: A Future Technology
		2.2.1 QCA Cell
		2.2.2 QCA Wires
		2.2.3 Basic QCA Gates
			2.2.3.1 QCA Inverter Gate
			2.2.3.2 QCA Majority Gate
		2.2.4 QCA Clocking
		2.2.5 QCA Implementation Techniques
			2.2.5.1 Metal-Island QCA
			2.2.5.2 Semiconductor QCA
			2.2.5.3 Molecular QCA
			2.2.5.4 Magnetic QCA
		2.2.6 Logic Development: Irreversible / Traditional and Reversible Logic
	2.3 Designing of Adder
	2.4 Designing of Multiplexer and De-Multiplexer
		2.4.1 Multiplexer Designs
		2.4.2 De-Multiplexer Designs
	2.5 Designing of Flip-Flop
		2.5.1 D Flip-Flop
		2.5.2 T Flip-Flop
		2.5.3 JK Flip-Flop
	2.6 Designing of Memory Cell
	2.7 Summary of the Chapter
	References
3 An Optimized Approach of Designing Adders and Multiplexer in QCA
	3.1 Introduction
	3.2 QCA Terminology
	3.3 Few Combinational Logic Circuits in QCA
		3.3.1 Half Adder
		3.3.2 Full Adder
		3.3.3 Half Subtractor
		3.3.4 Full Subtractor
		3.3.5 Multiplexer
	3.4 PTM and Reliability Framework
		3.4.1 Computation for Half Adder
		3.4.2 Computation for Full Adder
		3.4.3 Computation for Half Subtractor
		3.4.4 Computation for Full Subtractor
		3.4.5 Computation for 2 × 1 Multiplexer
	3.5 Conclusion
	References
4 High-Speed Comparator and Parity Generator Towards Simplified Clocking Circuit in QCA Technology
	4.1 Introduction
	4.2 Background
		4.2.1 QCA Basics
		4.2.2 XOR Structures
		4.2.3 Comparator Designs
	4.3 Proposed QCA Designs
		4.3.1 Single-Bit Comparator Design
		4.3.2 Parity Generator Circuit
	4.4 Simulation Results and Analysis
	4.5 Conclusion
	References
5 Towards Effective Multiplexer Circuit Design in QCA Technology
	5.1 Introduction
	5.2 Background
		5.2.1 QCA Cell
		5.2.2 QCA Gates
		5.2.3 MUX Circuits
	5.3 The Developed MUX Circuits
		5.3.1 The Designed 2n:1 QCA MUX Circuit for N = 1
		5.3.2 The Designed 2n:1 QCA MUX Circuit for N = 2
		5.3.3 The Designed 2n:1 QCA MUX Circuit for N = 3
	5.4 The Results and Comparison
		5.4.1 The Simulation Results
		5.4.2 The Comparison
	5.5 Conclusions
	References
6 An Optimized Approach of Designing Register and Counter in QCA
	6.1 Introduction
	6.2 QCA Terminology
	6.3 Sequential Logic Circuits in QCA Technology
		6.3.1 D Flip-Flop
		6.3.2 T Flip-Flop
		6.3.3 Register
		6.3.4 Counter
	6.4 Power Estimation Using QCA-Pro
		6.4.1 Computation for D Flip-Flop
		6.4.2 Computation for T Flip-Flop
		6.4.3 Computation for 2-Bit PIPO
		6.4.4 Computation for 2-Bit Counter
	6.5 Conclusion
	References
7 QCA-Based Designs of Majority Gates, Flip-Flops and Polar Encoders
	7.1 Introduction
		7.1.1 Background
		7.1.2 QCA Basics
	7.2 Proposed 5-Input Majority Gate and D Flip-Flop
		7.2.1 Proposed 5-Input Majority Gate
		7.2.2 Proposed D Flip-Flop
		7.2.3 Comparisons
	7.3 Proposed XOR Gate and Polar Encoder
		7.3.1 Proposed XOR Gate
		7.3.2 Polar Encoders
		7.3.3 Comparisons
	7.4 Conclusions
	References
8 Physically Realizable Reversible Logic Gates in Beyond CMOS QCA Technology
	8.1 Introduction
	8.2 Clocking in QCA
	8.3 Clocking Schemes in QCA
	8.4 Reversible Logic and Reversible Gates
		8.4.1 Feynman Gate
		8.4.2 Toffoli Gate
		8.4.3 Fredkin Gate
		8.4.4 Peres Gate
	8.5 Reversible Logic QCA Gates
	8.6 Conclusion
	References
9 Design of New Circuits for Reversible ALU in QCA Technology
	9.1 Introduction
	9.2 Background
		9.2.1 QCA Cells
		9.2.2 QCA Wire
		9.2.3 QCA Gates
		9.2.4 QCA Clocking
		9.2.5 Related Works
	9.3 The Presented RALU Circuits
		9.3.1 The Developed RLU
		9.3.2 The First Proposed RALU
		9.3.3 The Second Proposed RALU
		9.3.4 The Third Proposed RALU
	9.4 Results and Comparison
		9.4.1 Simulation Results
			9.4.1.1 Results of the Developed RLU
			9.4.1.2 Simulation Results of First Developed RALU
			9.4.1.3 Simulation Results of Second Developed RALU
			9.4.1.4 Simulation Results of Developed Third RALU
		9.4.2 Comparison
	9.5 Conclusion
	References
10 Stick Diagram Representation for MQCA-Based Multiplexer
	10.1 Introduction
	10.2 Design of NML-Based Multiplexer Circuit
	10.3 Stick Diagram Model for Higher Bit Multiplexer
	10.4 Conclusion
	References
11 Fully Depleted Planar Bi-Layer Junctionless Transistor for Future Technology Node
	11.1 Introduction
	11.2 Device Structure and Operation
		11.2.1 Equilibrium and Non-Equilibrium Transport
	11.3 Results and Discussion
	11.4 Conclusion
	References
Index