Predictive Technology Model for Robust Nanoelectronic Design

9.1.1 Device Structure......Page 3
Predictive TechnologyModel for RobustNanoelectronic Design......Page 4
  9.1.4 Schottky Barrier Modeling......Page 7
  6.3.4 Coupling Capacitance between Parallel Lines......Page 9
 9.2 Interconnect Modeling......Page 11
  9.2.2 Capacitance and Inductance of CNT Interconnect......Page 13
Cover......Page 1
 Copyright......Page 5
  6.4.4 Cu Diffusion Barrier......Page 16
  8.3.2 Height-Affecting Rules......Page 6
 Foreword......Page 8
 Acknowledgements......Page 12
  9.3.1 Device Fabrication and Measurement......Page 15
 8.2 Transistor Types and Models......Page 2
Chapter 1: Introduction......Page 17
  4.2.3 Predictive Vth Variability Modeling......Page 19
 References......Page 22
 Preface......Page 10
 Contents......Page 14
  9.3.2 Model Based Extraction of Variations......Page 18
 References......Page 20
 2.1 PTM in Light of CMOS Scaling......Page 23
  2.2.1 Parameter Taxonomy......Page 26
  2.2.2 Prediction of Model Parameters......Page 27
  2.3.1 Verification and Prediction of I-V Characteristics......Page 31
  2.3.2 Impact of Process Variations......Page 33
 References......Page 38
 3.1 Strain Engineering in Scaled CMOS......Page 40
  3.1.1 Modeling of Stress Distribution in the Channel......Page 42
  3.1.2 Equivalent Mobility Model......Page 43
  3.1.3 Strain Induced Threshold Voltage Shift......Page 45
 3.2 High-k/Metal Gate and Multiple-Vth Devices......Page 47
 3.3 Modeling of the FinFET Structure......Page 51
 References......Page 54
Chapter 4: Statistical Extraction and Modeling of CMOS Variability......Page 57
 4.1 Variability Characterization and Extraction......Page 58
  4.1.1 Test Chip and In-Situ Measurement......Page 59
  4.1.2 Extraction and Decoupling of Variations......Page 60
  4.1.3 Verification and Statistical Analysis......Page 63
 4.2 Predictive Modeling of Threshold Variability......Page 68
  4.2.1 Simulation with Gate Slicing Method......Page 69
  4.2.2 Validation with Atomistic Simulations......Page 73
  4.2.3 Predictive Vth Variability Modeling......Page 75
 References......Page 78
Chapter 5: Modeling of Temporal Reliability Degradation......Page 81
 5.1 Static Aging Models......Page 83
  5.2.1 Cycle-to-Cycle Degradation Model......Page 86
  5.2.2 Long-Term Degradation Model......Page 87
  5.3.1 Sub-circuit for SPICE Simulation......Page 88
  5.3.2 Device and Circuit Performance Degradation......Page 89
 5.4 Interaction with Process Variations......Page 91
 References......Page 93
 6.1 Background of Interconnect Models......Page 95
 6.2 Modeling Principles......Page 97
  6.3.1 Model of the Line-to-Plate Capacitance......Page 101
  6.3.2 Role of Terminal Capacitance......Page 102
  6.3.4 Coupling Capacitance between Parallel Lines......Page 103
 6.4 Applications to General BEOL Structures......Page 104
  6.4.1 Physical Effects with Multiple Electrodes......Page 106
  6.4.2 Modeling of the Coupling Capacitance......Page 107
  6.4.3 Revisiting the Line-to-Plate Capacitance......Page 108
  6.4.4 Cu Diffusion Barrier......Page 110
  6.4.5 Air Gap......Page 112
 References......Page 116
Chapter 7: Design Benchmark with Predictive Technology Model......Page 118
 7.1 Customization of PTM......Page 119
 7.2 Exploratory Design of 22nm CMOS Circuits......Page 121
  7.2.1 Ring Oscillator Delay and Energy......Page 123
  7.2.2 Performance of Sequential Elements......Page 124
  7.2.3 Impact of BEOL Scaling......Page 125
 7.3 Scaling Trend of Circuit Resilience......Page 128
 References......Page 131
 8.1 Introduction......Page 133
 8.2 Transistor Types and Models......Page 134
 8.3 Front-End Design Rules......Page 136
  8.3.1 Width-Affecting Rules......Page 137
  8.3.2 Height-Affecting Rules......Page 138
  8.3.3 Antenna Rules......Page 140
  8.4.1 Via Rules......Page 143
  8.4.2 Variable Spacing and Density Rules......Page 144
  8.4.3 Metal Stack......Page 145
 8.5 Lithography Simulation Model......Page 147
 8.6 The Future of Process Design Kits......Page 149
 References......Page 150
Chapter 9: Predictive Modeling of Carbon Nanotube Devices......Page 153
  9.1.1 Device Structure......Page 155
  9.1.2 Zone-folding Approximation......Page 156
  9.1.3 Surface-potential Based Modeling......Page 157
  9.1.4 Schottky Barrier Modeling......Page 159
  9.1.5 Transistor Model Extraction and Validation......Page 162
 9.2 Interconnect Modeling......Page 163
  9.2.1 CNT Interconnect Resistance......Page 164
  9.2.2 Capacitance and Inductance of CNT Interconnect......Page 165
  9.2.3 Interconnect Model Extraction and Validation......Page 166
  9.3.1 Device Fabrication and Measurement......Page 167
  9.3.2 Model Based Extraction of Variations......Page 170
 9.4 Design Insights with CNT Devices......Page 172
 References......Page 175
Chapter 10: Predictive Technology Model for Future Nanoelectronic Design......Page 177
Index......Page 179