Power Integrity for I/O Interfaces: With Signal Integrity/Power Integrity Co-Design

Cover......Page 1
Contents......Page 6
Foreword......Page 14
Preface......Page 16
Acknowledgments......Page 20
About the Authors......Page 22
 1.1 Digital Electronic System......Page 24
 1.2 I/O Signaling Standards......Page 25
  1.2.1 Single-Ended and Differential Signaling......Page 26
 1.3 Power and Signal Distribution Network......Page 28
 1.4 Signal and Power Integrity......Page 29
 1.5 Power Noise to Signal Coupling......Page 31
  1.5.2 Chip-Level SSO Coupling......Page 32
  1.5.3 Interconnect Level SSO Coupling......Page 33
 1.6 Concurrent Design Methodology......Page 35
 References......Page 36
 2.1 Single-Ended Drivers and Receivers......Page 38
  2.1.1 Open Drain Drivers......Page 39
  2.1.2 Push-Pull Driver and Receiver......Page 40
  2.1.4 Current Profiles in a Push-Pull Driver......Page 41
  2.1.5 Noise for Push-Pull Driver......Page 48
 2.2 Differential Drivers and Receivers......Page 49
  2.2.1 Termination Schemes for Differential System......Page 51
  2.2.2 Current Profiles in Half Differential Driver......Page 53
  2.2.3 Noise for Half Differential Driver......Page 55
 2.3 Prior Stages of I/O Interface......Page 57
 References......Page 58
 3.1 Electromagnetic Effects on Signal/Power Integrity......Page 60
 3.2 Electromagnetic Theory......Page 62
  3.2.1 Maxwell’s Equations......Page 63
 3.3 Transmission Line Theory......Page 69
 3.4 Interconnection Network Parameters: Z,Y,S and ABCD......Page 78
  3.4.1 Impedance Matrix [Z]......Page 79
  3.4.3 The Scattering Matrix [S]......Page 80
  3.4.4 The Scattering Matrix [S] with Arbitrary Loads......Page 82
  3.4.5 Relation Between Scattering Matrix [S] and Y/Z/ABCD Matrix......Page 84
  3.5.2 Parameter Conversion Singularity......Page 87
  3.5.4 Passivity......Page 88
 References......Page 90
 4.1 PCB Technology......Page 92
 4.2 Package Types......Page 93
  4.3.1 PCB PDN......Page 96
  4.3.2 Package Power Distribution Network......Page 115
  4.3.3 On-Chip Power Network......Page 116
  4.4.1 PCB/ Package Physical Signal Routing......Page 120
  4.4.2 Package Signal Distribution Network......Page 130
  4.4.3 PCB/Package Material Properties......Page 131
  4.4.4 On-Chip Signal Network......Page 135
 4.5 Interaction Between Interconnect Systems......Page 138
  4.5.2 Referencing: Single-Ended and Differential Signaling......Page 139
  4.5.3 Power to Signal Coupling......Page 141
 4.6 Modeling Tools for the PDN and Signal Networks......Page 142
 References......Page 145
Chapter 5 Frequency Domain Analysis......Page 150
 5.1 Signal Spectrum......Page 151
  5.1.1 Fourier Transform Interpretation......Page 155
  5.1.2 Important Properties of the Fourier Transform......Page 157
  5.1.3 FFT of Power Noise......Page 164
  5.1.4 Convolution and Filtering......Page 165
 5.2 Signal and Power Integrity Applications......Page 166
  5.2.1 S-Parameters with Global and Local Ground......Page 168
 5.3 Power Distribution Network Design in Frequency Domain......Page 170
  5.3.1 Impedance Response Z[sub(11)]......Page 171
  5.3.2 Impedance Targets for I/O Interface......Page 173
  5.3.3 PDN Design Example......Page 176
  5.3.4 On-Chip Power Delivery: Modeling and Characterization......Page 181
  5.3.5 Insertion Loss and Voltage Transfer Function......Page 189
  5.3.6 SSO in Frequency Domain......Page 191
  5.3.7 Power-to-Signal Coupling......Page 193
 5.4 Signal Network Design in Frequency Domain......Page 194
  5.4.1 Frequency Domain Optimization......Page 195
  5.4.2 Simulation and Correlation of Signal Network......Page 197
  5.4.3 Case Study: Crosstalk Amplification by Resonance......Page 198
  5.4.4 Differential Signaling in Frequency Domain......Page 207
 References......Page 213
 6.1 Time Domain Modeling and Simulation......Page 216
  6.1.1 Transient Simulations......Page 218
  6.1.2 Buffer Modeling......Page 219
  6.2.1 Power Delivery Time Domain Specification......Page 221
  6.2.2 Controllable Design Variables for Optimization......Page 223
  6.3.1 VR Tolerance and IR Drop......Page 227
  6.3.2 AC Noise Analysis......Page 230
  6.3.3 Internal Circuits......Page 232
  6.3.4 Final Stage Circuits......Page 233
  6.3.5 Single-Ended Systems......Page 235
  6.3.6 Differential Systems......Page 240
  6.3.7 Logic Stage......Page 243
 6.4 Jitter Impact for Time Domain Analysis......Page 244
  6.4.1 Jitter Impact Due to PDN Noise......Page 245
  6.4.2 Jitter Due to the SSO......Page 246
 References......Page 254
Chapter 7 Signal/Power Integrity Interactions......Page 256
 7.1 Background......Page 257
 7.2 Root Cause Analysis......Page 259
 7.3 SSO Coupling Mechanism......Page 261
 7.4 Case Study I: DDR2 800 Control Signal......Page 264
  7.4.1 Noise Source......Page 266
  7.4.2 Coupling Mechanism......Page 267
  7.4.3 Resonant Structure on Control Networks......Page 268
  7.4.4 Proposed Solutions......Page 270
 7.5 Case Study II: DDR2 667 Vref Bus......Page 271
  7.5.2 Coupling Mechanism......Page 272
  7.5.3 Resonance Structure......Page 273
  7.5.4 Proposed Solutions......Page 275
 7.6 Referencing/Stitching/Decoupling Effects–Single-Ended Interface......Page 281
 7.7 Stitching Effects—Differential Interface......Page 286
  7.7.1 VNA Measurement Results......Page 290
  7.7.2 Modeling and Measurement Correlations......Page 296
  7.7.3 System-Level Impact Evaluation......Page 297
  7.8.1 Power Islands Radiation......Page 299
 References......Page 305
Chapter 8 Signal/Power Integrity Co-Analysis......Page 308
 8.1 Identifying Controllable Parameters......Page 309
  8.2.1 Modeling SI-PI Compatible Buffers......Page 311
  8.2.2 Modeling On-Chip Passive Components......Page 313
  8.2.4 Model Check and Integration......Page 314
  8.2.6 PDN Resonance Excitation of Driver Bit Pattern......Page 315
  8.2.7 Worst-Case Eye......Page 317
  8.2.8 Running SI-PI Co-Simulation......Page 319
  8.3.1 Time Domain Analysis......Page 324
  8.3.2 Eye Diagram Analysis......Page 331
  8.3.3 Linear Interaction Indicator......Page 332
 8.4 SI-PI Co-Simulation and Co-Analysis Flow: Summary......Page 344
 References......Page 345
 9.1 Frequency Domain Characterization......Page 348
  9.1.1 Vector Network Analyzer (VNA)......Page 349
  9.1.2 Smith Chart......Page 350
  9.1.3 Low-Impedance VNA Measurement for Power Delivery Network......Page 352
  9.1.4 On-Chip Characterization......Page 358
  9.1.5 Pad Capacitance Characterization......Page 373
  9.1.6 Power Delivery-to-Signal Coupling Measurement......Page 376
  9.2.1 Need for an Equivalent Circuit Model......Page 378
  9.2.2 Extraction Methodology......Page 380
  9.2.3 Extraction Examples......Page 381
  9.3.1 Time Domain Reflectometry (TDR)......Page 384
  9.3.2 PDN Noise Measurement......Page 395
  9.3.3 SSO Coupling Measurement in Time Domain......Page 399
  9.3.4 Jitter Measurement......Page 402
 References......Page 403
 C......Page 406
 D......Page 407
 F......Page 408
 I......Page 409
 M......Page 410
 O......Page 411
 P......Page 412
 Q......Page 413
 S......Page 414
 T......Page 415
 Z......Page 416