Phase-Locking in High-Performance Systems: From Devices to Architectures

Table of Contents......Page 1
Original Contributions......Page 7
A study of phase noise in CMOS oscillators......Page 74
Corrections to-A General Theory of Phase Noise in Electrical Oscillators......Page 87
Jitter and phase noise in ring oscillators......Page 88
On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops......Page 103
Physical processes of phase noise in differential LC oscillators......Page 112
A general theory of phase noise in electrical oscillators......Page 116
A study of oscillator jitter due to supply and substrate noise......Page 132
A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers.pdf......Page 139
A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mbps GFSK modulation.pdf......Page 152
A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver.pdf......Page 165
A Fully Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS.pdf......Page 173
A modeling approach for spl Sigma-spl Delta fractional-N frequency synthesizers allowing straightforward noise analysis.pdf......Page 180
A Stabilization Technique for Phase-Locked Frequency Synthesizers.pdf......Page 191
An Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time.pdf......Page 198
Fast Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector.pdf......Page 211
Low-Power Dividerless Frequency Synthesis Using Aperture Phase Detection.pdf......Page 219
A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I Q Matching.pdf......Page 227
A 2.6-GHz OR 5.2-GHz Frequency Synthesizer in 0.4 um CMOS Technology.pdf......Page 234
A CMOS monolithic sigmadelta-controlled fractional-N frequency synthesizer for DCS-1800.pdf......Page 241
A 960-Mbps per pin interface for skew-tolerant bus using low jitter PLL.pdf......Page 251
A dual-loop delay-locked loop using multiple voltage-controlled delay lines.pdf......Page 261
A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V or 5 V operation.pdf......Page 269
A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz.pdf......Page 274
A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM.pdf......Page 281
A low-noise fast-lock phase-locked loop with adaptive bandwidth control.pdf......Page 290
A Portable Digital DLL for High-Speed CMOS Interface Circuits.pdf......Page 299
A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM.pdf......Page 312
A Semidigital Dual Delay-Locked Loop.pdf......Page 316
A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle.pdf......Page 326
Active GHz clock network using distributed PLLs.pdf......Page 333
Active GHz clock network using distributed PLLs-conf.pdf......Page 341
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance.pdf......Page 345
CMOS DLL-Base 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator.pdf......Page 353
Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques.pdf......Page 360
A 1.5V 86 mW per ch 8-Channel 622-3125-Mbps per ch CMOS SerDes Macrocell with Selectable Mux or Demux Ratio.pdf......Page 370
A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation.pdf......Page 373
A Fully Integrated VCO at 2 GHz......Page 381
A Simple Precharged CMOS Phase Frequency Detector......Page 386
A 10-Gbps CMOS clock and data recovery circuit with a half-rate linear phase detector.pdf......Page 426
A 40-Gbps integrated clock and data recovery circuit in a 50-GHz f t silicon bipolar technology.pdf......Page 436
Rotary Traveling-Wave Oscillator Arrays:A New Clock Technology......Page 391
A 1.6-GHz Dual Modulus Prescaler Using the ExtendedTrue-Single-Phase-Clock CMOS Circuit Technique (E-TSPC)......Page 403
A CMOS Monolithic 
-Controlled Fractional-NFrequency Synthesizer for DCS-1800......Page 409
A Family of Low-Power Truly Modular Programmable Dividersin Standard 0.35-m CMOS Technology......Page 419
A 10-Gbps CMOS Clock and Data Recovery Circuit with Frequency Detection.pdf......Page 433
A Fully Integrated 40-Gbps Clock and Data Recovery IC With 1 4 DEMUX in SiGe Technology.pdf......Page 441
A fully integrated SiGe receiver IC for 10-Gbps data rate.pdf......Page 450
Clock and Data Recovery IC for 40-Gbps Fiber-Optic Receiver.pdf......Page 459
Clock Data Recovery PLL Using Half-Frequency Clock.pdf......Page 465
SiGe clock and data recovery IC with linear-type PLL for 10-Gbps SONET application.pdf......Page 469
A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability.pdf......Page 476
A 2.5-Gbps clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs.pdf......Page 486
A 10-Gbps CDR or DEMUX with LC delay line VCO in 0.18-spl mu per m CMOS.pdf......Page 494
A 0.5-µm CMOS 4.0-Gbps serial link transceiver with data recovery using oversampling.pdf......Page 503