PCI Express Card Electromechanical Specification, Revision 4.0, Version 0.9

November 27, 2018
1. Introduction
	1.1. Terms and Definitions
	1.2. Reference Documents
	1.3. Specification Contents
	1.4. Objectives
	1.5. Electrical Overview
	1.6. Mechanical Overview
	1.7. 150 W Overview
	1.8. 225 W and 300 W Add-in Card Overview
2.  Auxiliary Signals
	2.1. Reference Clock
		2.1.1. Low Voltage Swing, Differential Clocks
		2.1.2. Spread Spectrum Clocking (SSC)
		2.1.3. REFCLK AC Specifications
		2.1.4. REFCLK Phase Jitter Specification for 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0GT/s Signaling Support
	2.2. PERST# Signal
		2.2.1. Initial Power Up (G3 to S0)
		2.2.2. Power Management States (S0 to S3/S4 to S0)
		2.2.3. Power Down
	2.3. WAKE# Signal
	2.4. SMBus (Optional)
		2.4.1. Capacitive Load of High-power SMBus Lines
		2.4.2. Minimum Current Sinking Requirements for SMBus Devices
		2.4.3. SMBus “Back Powering” Considerations
		2.4.4. Power-on Reset
	2.5. JTAG Pins (Optional)
	2.6. PWRBRK# Signal (Optional)
	2.7. Auxiliary Signal Parametric Specifications
		2.7.1. DC Specifications
		2.7.2. AC Specifications
3. Hot insertion and Hot removal
	3.1. Scope
	3.2. Presence Detect
4. Electrical Requirements
	4.1. Power Supply Requirements
	4.2. Power Consumption
	4.3. Power Budgeting Capability
	4.4. Power Supply Sequencing
	4.5. Power Supply Decoupling
	4.6. Electrical Topologies and Link Definitions
		4.6.1. Topologies
		4.6.2. Link Definition
	4.7. Electrical Budgets
		4.7.1. AC Coupling Capacitors
		4.7.2. Insertion Loss Values (Voltage Transfer Function)
		4.7.3. Jitter Values
		4.7.4. Crosstalk
		4.7.5. Lane-to-Lane Skew
		4.7.6. Transmitter Equalization
		4.7.7. Skew within the Differential Pair
		4.7.8. Differential Data Trace Impedance
		4.7.9. Differential Data Trace Propagation Delay
		4.7.10. Add-in Card Insertion Loss Limit for 16.0 GT/s
	4.8. Eye Diagrams at the Add-in Card Interface
		4.8.1. Add-in Card Transmitter Path Compliance Eye Diagram at 2.5 GT/s
		4.8.2. Add-in Card Transmitter Path Compliance Eye Diagrams at 5.0 GT/s
		4.8.3. Add-in Card Transmitter Path Compliance Eye Diagrams at 8.0 GT/s
		4.8.4. Add-in Card Transmitter Path Compliance Eye Diagrams at 16.0 GT/s
		4.8.5. Add-in Card Transmitter Path Pulse Width Jitter at 16.0 GT/s
		4.8.6. Add-in Card Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s
		4.8.7. Add-in Card Minimum Receiver Path Sensitivity Requirements at 5.0 GT/s
		4.8.8. Add-in Card Minimum Receiver Path Sensitivity Requirements at 8.0 GT/s
		4.8.9. Add-in Card Minimum Receiver Path Sensitivity Requirements at 16.0 GT/s
		4.8.10. System Board Transmitter Path Compliance Eye Diagram at 2.5 GT/s
		4.8.11. System Board Transmitter Path Compliance Eye Diagram at 5.0 GT/s
		4.8.12. System Board Transmitter Path Compliance Eye Diagram at 8.0 GT/s
		4.8.13. System Board Transmitter Path Compliance Eye Diagram at 16.0 GT/s
		4.8.14. System Board Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s
		4.8.15. System Board Minimum Receiver Path Sensitivity Requirements at 5.0 GT/s
		4.8.16. System Board Minimum Receiver Path Sensitivity Requirements at 8.0 GT/s
		4.8.17. System Board Minimum Receiver Path Sensitivity Requirements at 16.0 GT/s
5. 150 W, 225 W, and 300 W Add-in Card Power
	5.1. 150 W Add-in Card Power-Up Sequencing
	5.2. 225 W and 300 W Add-in Card Power-Up Sequencing
6. Card Connector Specification
	6.1. Connector Pinout
	6.2. Connector Interface Definitions
	6.3. Signal Integrity Requirements and Test Procedures
		6.3.1. Signal Integrity Requirements
		6.3.2. Signal Integrity Requirements and Test Procedures for 2.5 GT/s Support
		6.3.3. Signal Integrity Requirements and Test Procedures for 5.0 GT/s Support
			6.3.3.1 Test Fixture Requirements
		6.3.4. Signal Integrity Requirements and Test Procedures for 8.0 GT/s Support
			6.3.4.1 Test Fixture Requirements
		6.3.5. Signal Integrity Requirements and Test Procedures for 16.0 GT/s Support
			6.3.5.1 Test Fixture Requirements
	6.4. Connector Environmental and Other Requirements
		6.4.1. Environmental Requirements
		6.4.2. Mechanical Requirements
		6.4.3. Current Rating Requirement
		6.4.4. Additional Considerations
7. PCI Express 2 x 3 Auxiliary Power Connector Definition
	7.1. 6-Position Power Connector System Performance Requirements
	7.2. 6-Position PCB Header
		7.2.1. 6-Position R/A Thru-Hole PCB Header Assembly
		7.2.2. 6-Position R/A Thru-Hole Header Recommended PCB Footprint
		7.2.3. 6-Position R/A SMT PCB Header Assembly
		7.2.4. 6-Position R/A SMT Header Recommended PCB Footprint
	7.3. 6-Position Cable Assembly
	7.4. Connector Mating-Unmating Keepout Area (Latch Lock Release)
	7.5. 6-Position Power Connector System Pin Assignment
	7.6. Additional Considerations
8. PCI Express 2 x 4 Auxiliary Power Connector Definition
	8.1. 2 x 4 Auxiliary Power Connector Performance Requirements
	8.2. 2 x 4 Receptacle
		8.2.1. Connector Drawing
		8.2.2. PCB Footprint
	8.3. Cable Assembly
	8.4. Connector Mating-Unmating Keepout Area (Latch Lock Release)
	8.5. 2 x 4 Auxiliary Power Connector System Pin Assignment
	8.6. Additional Considerations
9. Add-in Card Form Factors and Implementation
	9.1. Add-in Card Form Factors
	9.2. Add-in Card Layout Requirements and Recommendations for 16.0 GT/s Operation
		9.2.1. Voiding and Planes Under Edge-fingers
		9.2.2. No Add-in Card Depopulated or Floating Edge-fingers
		9.2.3. Edge-finger Length and Outer Layer Keepout
		9.2.4. Add-in Card Adjacent Edge-finger Ground Vias
		9.2.5.  Joined Edge-finger Ground Vias
		9.2.6. Auxiliary Signal Conductor AC Match Termination
	System Board Requirements for 16.0 GT/s Operation
		9.3.1. Sentry Ground Vias Adjacent to Auxiliary Signal Vias
	9.4. Connector and Add-in Card Locations
	9.5. Card Interoperability
	9.6.  10 W/25 W/75 W/150 W Thermal Characterization
	9.7. 150 W Thermal Management
10. PCI Express 225 W/300 W Add-in Card Thermal and Acoustic Management
	10.1. Inlet Temperature
	10.2. Card Thermal Characterization Procedure
	10.3. Acoustic Management
		10.3.1. Background and Scope
		10.3.2. Card Acoustic Characterization Procedure
		10.3.3. Acoustic Recommendations and Guidelines
11. Adapter Add-in Card Thermal Reporting
	11.1. Airflow Impedance (AFI) Level
	11.2. Maximum Thermal (MaxTherm) Level
	11.3. Degraded Thermal (DTherm) Level
	11.4. MaxAmbient
INSERTION LOSS VALUES (VOLTAGE TRANSFER FUNCTION) (INFORMATIONAL ONLY)
TEST CHANNEL SCATTERING PARAMETERS
	8.0 GT/s Test Channels
		16.0 GT/s Test Channels
THERMAL DATA COLLECTION AND TEST PROCEDURE
ACKNOWLEDGEMENTS