Noise in Nanoscale Semiconductor Devices

Contents
Origins of 1/f Noise in Electronic Materials and Devices: A Historical Perspective
	1 Introduction
	2 Number Fluctuations: Application to MOSFETs
	3 Mobility Fluctuations: Hooge\'s Model
	4 Noise in Metals: Dutta–Horn Model
	5 MOS Transistors: Defect Densities and Microstructure
	6 GaN/AlGaN HEMTs: Number Fluctuations
	7 SiC MOS Devices
	8 Two-Dimensional Materials
	9 Summary and Conclusions
	References
Noise and Fluctuations in Fully Depleted Silicon-on-InsulatorMOSFETs
	Abbreviations
	1 Introduction
	2 Theoretical Background
		2.1 Origin of Low-Frequency Noise in MOSFETs
			Carrier Number Fluctuations and Correlated Mobility Fluctuations (CNF/CMF)
			Hooge Mobility Fluctuations (HMF)
			Impact of Access Resistance
			Random Telegraph Noise (RTN)
		2.2 Noise Model Development and Challenges
			Multi-Interface CNF Approach
			Two-Interface CNF/CMF Modeling
	3 Noise Characterization in FD-SOI MOSFETs
		3.1 Flicker Noise in FD-SOI MOSFETs
			Front/Back Coupling Effects
			Impact of Channel Geometry on RCS
		3.2 Generation–Recombination Noise
		3.3 Noise Variability
			General Properties of LFN Variability
			Variability Comparison Between Different Technology Nodes
			Statistical LFN/RTN Characterization Methods
			Dependence on Frequency, Gate Bias, and Temperature
	4 From Noise Modeling to Circuit Simulations
		4.1 Noise Model Implementation
			Using Verilog-A for Noise Modeling
			Implementing the Two-Interface CNF/CMF Model
			Defect-Aware Time-Domain Module
		4.2 Impact of LFN/RTN on Circuit Operation
			Phase Noise in FD-SOI Ring Oscillator Circuits
			The SRAM Cell as a Circuit Reference
			“Periodic Transient Noise” Approach
			Defect-Aware Time-Domain Simulations
	5 Conclusion
	References
Noise in Resistive Random Access Memory Devices
	1 Introduction
	2 Random Telegraph Noise: Measurement and Analysis Tools
		2.1 RTN Statistics
		2.2 RTN Classifications
		2.3 RTN Analysis Tools
			Histogram and Time-Lag Plots
			Hidden Markov Model
			Factorial Hidden Markov Model
			Other Approaches and Open Challenges
		2.4 Guidelines for RTN Measurement and Analysis in RRAM Devices
	3 Statistical Investigation of the RTN Physical Mechanisms
		3.1 The Role of Atomic Defects
		3.2 Charge Transport in RRAM Devices
		3.3 Physics of RTN in HRS
		3.4 Physics of RTN in LRS
	4 Compact Model of RTN
		4.1 Statistical Model for the Fluctuation Amplitude
			The Fluctuation Amplitude in HRS
			The Fluctuation Amplitude in LRS
		4.2 RTN Capture and Emission Times
		4.3 Compact Model Validation
		4.4 Compact Model Applications and Advanced Circuit Design
			Design of RRAM Circuits Considering RTN
			Design of an RTN-Based Random Number Generator Circuit
	5 Conclusions
	References
Systematic Characterization of Random Telegraph Noise and Its Dependence with Magnetic Fields in MOSFET Devices
	1 Introduction
	2 RTN Time Signature Characterization
		2.1 Determination of the Trap Location and Back-Biased Devices
	3 Low-Frequency Noise Characterization
	4 Optimized Systematic Characterization Protocol
		4.1 Determination of the Optimum Bias Condition
		4.2 Identifying the Number of Traps in the RTN Signals
		4.3 Systematic Experimental Protocol
		4.4 On-Wafer Trap Distribution
	5 Magnetic Field Effect
		5.1 Magnetic Field Effect on Trapping Dynamics
	6 Conclusion
	References
Principles and Applications of Ig-RTN in Nano-scaled MOSFET
	1 Introduction
	2 Device Preparations
	3 Methodology of Extracting Trap Depth and Energy Level
		3.1 Ig-RTN
		3.2 Single-Layer Oxide
		3.3 Bilayer Oxide
	4 Characteristics of Ig-RTN During Development of Dielectric Soft Breakdown
		4.1 Signals of Ig-RTN Waveforms
		4.2 Ig-RTN After Soft Breakdown of MOSFET
	5 BTI-Induced RTN Trap Depth
		5.1 Observation on RTN Trap Distribution in an nMOSFET During BTI Stress
		5.2 Profile of the RTN-Trap Paths in MOSFET During BTI Stress
	6 Discovery of a New Breakdown: Dielectric-Fuse Breakdown in MOSFET and its Applications
		6.1 Investigation of Dielectric-Fuse Breakdown
		6.2 Dielectric Fuse Breakdown of HKMG and Poly-Si nMOSFET
		6.3 Dielectric-Fuse Breakdown OTP Cells
	7 Conclusions
	References
Random Telegraph Noise in Flash Memories
	1 Introduction
	2 Experimental Data
	3 Models
	4 Effect on Programmed VT Distribution
	5 3D Cells
		5.1 Experimental
		5.2 Models
	6 Conclusions
	References
Advanced Electrical Characterization of Single Oxide Defects Utilizing Noise Signals
	1 Introduction
		1.1 Random Telegraph Noise
		1.2 Link Between RTN and 1/f Noise
	2 Measurements
		2.1 Number of Observations
	3 Defect Parameter Extraction
		3.1 Histogram and Time Lag Plots
		3.2 Edge Detection
		3.3 Hidden Markov Models
	4 Oxide Defect Modeling
	5 Defect Characterization
		5.1 TCAD Simulation
		5.2 First-Order Calculations
	6 TDDS
		6.1 Measurement
		6.2 Measurement Limitations
		6.3 Defect Parameter Extraction
	7 Link Between RTN and TDDS
	8 Summary
	References
Measurement and Simulation Methods for Assessing SRAM Reliability Against Random Telegraph Noise
	1 Introduction
	2 Individual FET Characterization
	3 Accelerated SRAM Test
	4 RTN Monte Carlo Simulation
	5 Reliability Extrapolation
	6 Conclusion and Remarks
	References
Random Telegraph Noise Under Switching Operation
	1 Introduction
	2 Impact of Random Telegraph Noise on CMOS Logic Circuit Reliability
		2.1 Low-Frequency Noise and RTN
		2.2 RTN Time Constant
		2.3 Trap Density
		2.4 RTN Amplitude
		2.5 Impact on Logic Circuit
		2.6 Test Structure for RTN Impact Evaluation
		2.7 Measurement Results of Logic Delay Fluctuation
		2.8 Impact of RTN on Logic Circuit Reliability
		2.9 Comparison of RTN and Process Variation
		2.10 Summary
	3 Substrate Bias and Temperature Effect on Random Telegraph Noise
		3.1 Substrate Bias Effect on RTN
		3.2 Temperature Effect on RTN
		3.3 Design of Test Structure
			Test Chip
			RO Design
		3.4 Measurement Results
			Delay Fluctuations at Different Temperatures
			Correlation Across Temperatures
			Distribution of Delay Fluctuation
			Impact on Circuit Reliability
		3.5 Summary
	4 RTN Parameter Extraction Under Switching Operation
		4.1 Gate Delay Evaluation
		4.2 Test Structure
		4.3 RTN Parameter Extraction
		4.4 RTN Examples
		4.5 Amplitude Distribution
		4.6 Trap Density
		4.7 Summary
	5 Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model
		5.1 RTN Mechanism and Model Based on Physics
		5.2 Charge Trapping Model to MOSFET
		5.3 RTN Circuit Simulation Method Using CTM
		5.4 Simulation Results of RTN-Induced Drain Current and Frequency Fluctuation
			RTN-Induced Drain Current Fluctuation of NMOSFETs
			The Distribution of RTN-induced Frequency Fluctuation in Ring Oscillators (ROs)
		5.5 Summary
	6 Conclusion
	References
Low-Frequency Noise in III –V, Ge, and 2D Transistors
	1 Introduction
	2 Low-Frequency Noise in Near-Ballistic III–V MOSFETs
	3 Low-Frequency Noise in Near-Ballistic Ge MOSFETs
	4 Low-Frequency Noise in 2D Transistors
		4.1 Low-Frequency Noise in MoS2 transistors
		4.2 Low-Frequency Noise in BP Transistors
	5 Conclusion
	References
Detection and Characterization of Single Defects in MOSFETs
	1 Analysis of Single Interface Defects by the Charge Pumping Method
		1.1 Introduction
		1.2 Conventional CP Theory and Some Useful Applications of the CP Method
		1.3 Detection and Characterization of Single Interface Defects
			Fundamental Defect Counting: Separation of CP Current into Components from each Individual Defect
			CP Current from a Genuine Single Interface Defect
			Amphoteric Nature of Interface Defects
			Two Different Energy Levels in a Single Interface Defect
			Density of States of Single Interface Defects
		1.4 Actual Number of Interface Defects Involved in MOSFETs
			Comparison Between the Actual Number of Defects and the Values Determined by the Conventional CP Theory
			Coulomb Interaction Between Defects
		1.5 Fundamental Refinement of CP Theory
	2 Characterization of Individual Oxide Defects Using Charging History Effects in RTN
		2.1 Introduction
		2.2 Evaluation of Individual Oxide Defects Using Drain Current Histograms
			Validity of the Histogram Method
			Application to Two-Defect RTN: Simplicity and Usefulness of the Histogram Method
		2.3 Charging History RTN Method to Characterize Individual Oxide Defects
		2.4 Application of the CH-RTN Method to Multi-Defect RTN
			Determination of the Number and Charging Conditions of Oxide Defects
			Characterization of Each Individual Oxide Defects in Multi-Defect RTN
	3 Summary
	References
Random Telegraph Noise Nano-spectroscopy in High- Dielectrics Using Scanning Probe Microscopy Techniques
	1 Introduction
	2 Random Telegraph Noise in Dielectrics and Its Characterization
	3 Challenges of Device-Level RTN Spectroscopy
	4 Sample and Instrumentation Requirements for Defect Nano-Spectroscopy Using SPM
	5 Measurement of Random Telegraph Noise from Process- and Stress-Induced Defects
	6 Bias-Dependent RTN Spectroscopy
	7 Metastability of Oxygen Vacancy (VO) Defects
	8 RTN Analysis at Microstructural Sites
	9 Summary and Conclusions
	References
RTN and Its Intrinsic Interaction with Statistical Variability Sources in Advanced Nano-Scale Devices: A Simulation Study
	1 Introduction
	2 Computational Scheme and Device Specifications
		2.1 Template Devices
		2.2 The 3D Atomistic Simulator and RTN Trap Introduction
	3 Random Telegraph Noise and Statistical Variability
		3.1 The RTN Phenomena in Devices
		3.2 Intrinsic Interaction of RTN and Statistical Variability
		3.3 Dispersion of VT and Drain Current
	4 Fluctuation of τc, τe , and zT
		4.1 Randomness of Trap Location
		4.2 Randomness of Capture and Emission Time Constants
		4.3 Trap Interaction with Channel and Gate
	5 Summary
	References
Advanced Characterization and Analysis of Random Telegraph Noise in CMOS Devices
	1 Introduction
		1.1 RTN Phenomenology
	2 The Weighted Time Lag Method
	3 RTN Experimental Characterization Challenges
		3.1 Ultrafast Measurement Techniques
		3.2 Statistical RTN Characterization: Array-Based Solutions
	4 Other Applications of the w-TLP Method
		4.1 Evaluating the Intervals of Variations of the Drain Current in MOSFETs
		4.2 RTN and BTI Phenomena Identification in CMOS Devices
	5 Conclusions
	References
An Overview on Statistical Modeling of Random Telegraph Noise in the Frequency Domain
	1 Introduction
	2 Dielectric Defects as the Origin of the LFN
	3 Statistical Model for the Low-Frequency Noise
		3.1 Trap Impact on the MOSFET Drain Current
		3.2 Statistical Model for the Low-Frequency Noise in MOSFETs
		3.3 Area Dependence Under Simplified Conditions
		3.4 Short-Versus Long-Channel Devices and the Drain Bias Effect
		3.5 Short-Versus Long-Channel Devices with Halo Implants
		3.6 The Statistical LFN Model Versus Experimental Data
	4 Correlation Coefficient Analysis
		4.1 Frequency Autocorrelation
		4.2 Temperature Autocorrelation
	5 Summary and Conclusion
	References
Defect-Based Compact Modeling of Random Telegraph Noise
	1 Introduction
	2 Defect-Centric Modeling for BTI
		2.1 BTI as Time-Dependent Variability
			Statistical Moments and Normal Approximation
			Compound Poisson Distribution
			Origin of NBTI Variability
		2.2 Time Invariance of the Compound Poisson-Exponential Distribution
			Origin of Poisson Distributed Defects After Relaxation
			Origin of Poisson Distributed Defects During Stress
	3 Defect-Centric RTN Modeling
		3.1 Time Constants and Markov Processes
		3.2 Unconditional RTN Events
		3.3 Conditional RTN Events
		3.4 Noise Modeling
	4 Defect-Based Compact Modeling for RTN and BTI Variability
		4.1 Combined Dynamic BTI and RTN Emulation
		4.2 A Verilog-A Reliability Compact Model
		4.3 Model Input Parameters
			Defect Impact
			Defect Kinetics
		4.4 Initialization
		4.5 Simulation
			AC, DC, and Transient Analysis
			Monte Carlo and Corner Analysis
		4.6 Measurements and Calibration
	5 Conclusion
	References
Oxide Trap-Induced RTS in MOSFETs
	1 Introduction
	2 RTS Theory
	3 Charge Quantization Effects on RTS
	4 Experimental Setup and Measurement Techniques
	5 RTS Analyses
	6 RTS in nMOSFETs
	7 RTS in pMOSFETs
	8 Hot-Carrier Effects on RTS
	9 Comparison of RTS with Other Trap Characterization Techniques
	10 Discussions
	11 Conclusion
	References
Atomistic Modeling of Oxide Defects
	1 Introduction
	2 DFT in a Nutshell
		2.1 Many-Body Schrödinger Equation
		2.2 Hohenberg–Kohn Theorems
		2.3 Kohn–Sham Equations
		2.4 Exchange-Correlation Functionals and Pseudopotentials
	3 Modeling of Amorphous Structures
		3.1 Melt-Quench Technique
		3.2 Structural Verification
		3.3 Interface Models
		3.4 Formation Energies and Thermodynamic Trap Levels
	4 The Four-State NMP Model
		4.1 Experimental Evidence for the Four-State NMP Model
		4.2 State Diagram
		4.3 Transition Rates
			Thermal Transitions
			Nonradiative Multiphonon Transitions
	5 Defects in Amorphous SiO2
		5.1 Oxygen Vacancies
		5.2 Hydrogen-Induced Defects
			Hydrogen Bridge
			Hydroxyl-E\' Center
		5.3 Charge Trapping at Intrinsic Sites
		5.4 Comparison to Experimental Data
			Trap Level Distributions
			Defect Activation Energies
			Defect Volatility
	6 Defects in Amorphous HfO2
		6.1 Oxygen Vacancies
		6.2 Intrinsic Charge Trapping
		6.3 Trap Level Distributions
	7 Summary and Outlook
	References
The Langevin–Boltzmann Equation for Noise Calculation
	1 Introduction
	2 The Langevin–Boltzmann Equation
		2.1 Reciprocity
		2.2 Nyquist Theorem
		2.3 Analytical Solutions for a Homogeneous Resistor
		2.4 Numerical Solutions for an N+NN+ Resistor
	3 Balance Equations
		3.1 Analytical Solutions for a Homogeneous Resistor
		3.2 Numerical Solutions for an N+NN+ Resistor
	4 Conclusions
	References
Benchmark Tests for MOSFET Thermal Noise Models
	1 Introduction
	2 MOSFET Thermal Noise Models
		2.1 Fundamentals
		2.2 The Excess-Noise Controversy
		2.3 Excess Noise in Sub-100-nm CMOS Technology
	3 Measurement Details and Definitions
		3.1 Measurement System
		3.2 The White-Noise Gamma Factor
		3.3 The Fano Factor
		3.4 The β Factor
	4 Overview of Thermal Noise Benchmark Tests
		4.1 Benchmark Test #1: Drain Current Noise at VDS=0 V
		4.2 Benchmark Test #2: Gate Current Noise at VDS=0 V
		4.3 Benchmark Test #3: Correlation Coefficient at VDS=0 V
		4.4 Benchmark Test #4: Drain Current Noise in Weak Inversion
		4.5 Benchmark Test #5: Long-Channel Drain Current Noise in Saturation
		4.6 Benchmark Test #6: Long-Channel Gate Current Noise in Saturation
		4.7 Benchmark Test #7: Long-Channel Correlation Coefficient in Saturation
		4.8 Benchmark Test #8: Short-Channel Drain Current Noise in Saturation
		4.9 Benchmark Test #9: PMOS vs. NMOS
		4.10 Benchmark Test #10: Comparing Vth Flavors
	5 Application of Thermal Noise Benchmark Tests to a 28-nm CMOS Model Card
		5.1 The BSIM4 Thermal Noise Model
		5.2 Benchmark Test #1: the VDS=0 V Condition
		5.3 Benchmark Test #4: The Weak-Inversion Region
		5.4 Benchmark Tests #5, #8, #9, and #10: The Saturation Region
	6 Summary and Conclusion
	References
Index