Nanometer CMOS ICs: From Basics to ASICs, Third Edition

Foreword
Preface
Acknowledgements
Overview of Symbols
Explanation of Atomic-Scale Terms
List of Physical Constants
Contents
About the Author
1 Basic Principles
	1.1 Introduction
	1.2 The Field-Effect Principle
	1.3 The Inversion-Layer MOS Transistor
		1.3.1 The Metal-Oxide-Semiconductor (MOS) Capacitor
		1.3.2 The Inversion-Layer MOS Transistor
	1.4 Derivation of Simple MOS Formulae
	1.5 The Back-Bias Effect (The Influence of the Threshold Voltage on Transistor and Chip Behaviour)
	1.6 Factors Which Characterise the Behaviour of the MOSTransistor
	1.7 Different Types of MOS Transistors
	1.8 Parasitic MOS Transistors
	1.9 MOS Transistor Symbols
	1.10 Capacitances in MOS Structures
	1.11 Conclusions
	1.12 Exercises
	References
	General Basic Physics
	MOS Capacitances
2 Geometrical, Physical and Field-Scaling Impact on MOS Transistor Behaviour
	2.1 Introduction
	2.2 The Zero-Field Mobility
	2.3 Carrier Mobility Reduction
		2.3.1 Vertical and Lateral Field Carrier Mobility Reduction
		2.3.2 Stress-Induced Carrier Mobility Effects
	2.4 Channel Length Modulation
	2.5 Short- and Narrow-Channel Effects
		2.5.1 Short-Channel Effects
		2.5.2 Narrow-Channel Effect
	2.6 Temperature Influence on Carrier Mobility and ThresholdVoltage
	2.7 MOS Transistor Leakage Mechanisms
		2.7.1 Weak-Inversion (Subthreshold) Behaviour of the MOS Transistor
		2.7.2 Gate-Oxide Tunnelling
		2.7.3 Reverse-Bias Junction Leakage
		2.7.4 Gate-Induced Drain Leakage (GIDL)
		2.7.5 Hot-Carrier Injection and Impact Ionisation
		2.7.6 Overall Leakage Interactions and Considerations
	2.8 MOS Transistor Models and Simulation
		2.8.1 Worst-Case (Slow), Typical and Best-Case (Fast) Process Parameters and Operating Conditions
	2.9 Conclusions
	2.10 Exercises
	References
3 Manufacture of MOS Devices
	3.1 Introduction
	3.2 Different Substrates (Wafers) as Starting Material
		3.2.1 Wafer Sizes
		3.2.2 Standard CMOS Epi
		3.2.3 Crystalline Orientation of the Silicon Wafer
		3.2.4 Silicon-on-Insulator (SOI)
	3.3 Lithography in MOS Processes
		3.3.1 Lithography Basics
		3.3.2 Lithographic Extensions Beyond 30nm
		3.3.3 Accuracy Measurement of Lithographic Systems
		3.3.4 Mask Cost Reduction Techniques for Low-Volume Production
		3.3.5 Pattern Imaging
	3.4 Oxidation
	3.5 Deposition
	3.6 Etching
	3.7 Diffusion and Ion Implantation
	3.8 Planarisation
	3.9 Basic MOS Technologies
		3.9.1 The Basic Silicon-Gate nMOS Process
		3.9.2 The Basic Complementary MOS (CMOS) Process
		3.9.3 Sub-100nm CMOS Processes
			Shallow-Trench Isolation
			Retrograde-Well Formation
			Drain Extension and Halo Implant
			Silicides, Polycides and Salicides
			Ti/TiN Film
			Anti-reflective Coating (ARC)
			Contact (Re)fill
			Damascene Metal Patterning
		3.9.4 Further Transistor Scaling: From Planar to FinFETs
			Planar Devices
			3D and Alternative Devices
		3.9.5 CMOS Technologies Beyond 10nm
		3.9.6 Further Interconnect (BEOL and MEOL) Scaling
	3.10 Conclusions
	3.11 Exercises
	References
4 CMOS Circuit, Layout and Library Design
	4.1 Introduction
	4.2 The Basic nMOS Inverter
		4.2.1 Introduction
		4.2.2 The DC Behaviour
			Saturated Enhancement Load Transistor
			The Non-saturated Enhancement Load Transistor
			The Depletion Load Transistor
			The Resistive Load
		4.2.3 Comparison of the Different nMOS Inverters
		4.2.4 Transforming a Logic Function Into an nMOS Transistor Circuit
	4.3 Electrical Design of CMOS Circuits
		4.3.1 Introduction
		4.3.2 The CMOS Inverter
			The Electrical Behaviour of the CMOS Inverter
			Designing a CMOS Inverter
			Dissipation of a CMOS Inverter
			CMOS Buffer Design
			Noise Margins
	4.4 Digital CMOS Circuits
		4.4.1 Introduction
		4.4.2 Static CMOS Circuits
			The CMOS Transmission Gate (Pass Transistor)
			Pass-Transistor Logic
		4.4.3 Clocked Static CMOS Circuits
			Static Latches and Flip-Flops
		4.4.4 Dynamic CMOS Circuits
			Dynamic CMOS Latches, Shift Registers and Flip-Flops
			Critical Phenomena in Dynamic Circuits
		4.4.5 Other Types of CMOS Circuits
		4.4.6 Choosing a CMOS Implementation
			Power Dissipation
			Speed and Area
			Noise Immunity
		4.4.7 Clocking Strategies
	4.5 CMOS Input and Output (I/O) Circuits
		4.5.1 CMOS Input Circuits
		4.5.2 CMOS Output Buffers (Drivers)
	4.6 The Layout Process
		4.6.1 Introduction
		4.6.2 Layout Design Rules
		4.6.3 Stick Diagram
		4.6.4 Example of the Layout Procedure
		4.6.5 Guidelines for Layout Design
	4.7 Libraries and Library Design
	4.8 FinFET Layout
	4.9 Conclusions
	4.10 Exercises
	References and Further Reading
5 Special Circuits, Devices and Technologies
	5.1 Introduction
	5.2 CCD and CMOS Image Sensors
		5.2.1 Introduction
		5.2.2 Basic CCD Operation
		5.2.3 CMOS Image Sensors
		5.2.4 Conclusions on Image Sensors
	5.3 BICMOS Circuits
		5.3.1 Introduction
		5.3.2 BICMOS Technology
		5.3.3 BICMOS Characteristics
		5.3.4 BICMOS Circuit Performance
		5.3.5 Future Expectations and Market Trends
	5.4 Power MOSFETs
		5.4.1 Introduction
		5.4.2 Technology and Operation
		5.4.3 Applications
	5.5 Bipolar-CMOS-DMOS (BCD) Processes
	5.6 Conclusions
	5.7 Exercises
	References
6 Memories
	6.1 Introduction
	6.2 Serial Memories
	6.3 Content-Addressable Memories (CAM)
	6.4 Random-Access Memories (RAM)
		6.4.1 Introduction
		6.4.2 Static RAMs (SRAM)
			SRAM Block Diagram
			The SRAM Control Signals
			The SRAM Read Operation
			The SRAM Write Operation
			Static RAM Cells
			SRAM Applications
		6.4.3 Dynamic RAMs (DRAM)
			General Remarks on DRAM Architectures
		6.4.4 High-Performance DRAMs
			Fast Page Mode DRAM
			Extended Data Out DRAM
			Synchronous DRAMs
		6.4.5 Single- and Dual Port Memories
		6.4.6 Error Sensitivity
	6.5 Non-volatile Memories
		6.5.1 Introduction
		6.5.2 Read-Only Memories (ROM)
			ROM Cell with the Information in the ACTIVE Mask
			ROM Cell with the Information in the CONTACT Mask
			Comparison of the ACTIVE-Mask and CONTACT-Mask Programmed ROM Cells
		6.5.3 Programmable Read-Only Memories
			Introduction
			PROMs (Programmable Read-Only Memories)
			EPROMs
		6.5.4 EEPROMs and Flash Memories
			EEPROM
			Flash Memories
			Competing Flash Technologies
		6.5.5 Non-volatile RAM (NVRAM)
		6.5.6 BRAM (Battery RAM)
		6.5.7 FRAM, MRAM, PRAM (PCM) and RRAM
	6.6 Embedded Memories
	6.7 In-memory Computing
	6.8 Redundancy in Memories
	6.9 Classification of the Various Memories
	6.10 Conclusions
	6.11 Exercises
	References
	Further Reading
7 Very-Large-Scale Integration (VLSI) and ASICs
	7.1 Introduction
	7.2 Digital ICs
	7.3 Abstraction Levels for VLSI
		7.3.1 Introduction
		7.3.2 System Level
		7.3.3 Functional Level
		7.3.4 RTL Level
		7.3.5 Logic-Gate Level
		7.3.6 Transistor Level
		7.3.7 Layout Level
		7.3.8 Conclusions
	7.4 Digital VLSI Design
		7.4.1 Introduction
		7.4.2 The Design Trajectory and Flow
		7.4.3 Example of Synthesis from VHDL Description to Layout
		7.4.4 Floor-Planning
	7.5 The Use of ASICs
	7.6 Silicon Realisation of VLSI and ASICs
		7.6.1 Introduction
		7.6.2 Handcrafted Layout Implementation
		7.6.3 Bit-Slice Layout Implementation
		7.6.4 ROM, PAL and PLA Layout Implementations
		7.6.5 Cell-Based Layout Implementation
		7.6.6 (Mask-Programmable) Gate Array Layout Implementation
		7.6.7 Programmable Logic Devices (PLDs)
			Field-Programmable Gate Arrays (FPGAs)
			Complex Programmable Logic Devices (CPLDs)
			Programmability of FPGAs and CPLDs
		7.6.8 Embedded Arrays, Structured ASICs and Platform ASICs
			Structured ASICs and Platform ASICs
		7.6.9 Hierarchical Design Approach
		7.6.10 The Choice of a Layout Implementation Form
	7.7 Conclusions
	7.8 Exercises
	References
8 Less Power: A Hot Topic in IC Design
	8.1 Introduction
	8.2 Battery Technology Summary
	8.3 Sources of CMOS Power Consumption
	8.4 Technology Options for Low Power
		8.4.1 Reduction of Pleak by Technological Measures
			Active Well Biasing for Leakage Power Reduction
		8.4.2 Reduction of Pdyn by Technology Measures
		8.4.3 Reduction of Pdyn by Reduced Voltage Processes
	8.5 Design Options for Power Reduction
		8.5.1 Reduction of Pshort by Design Measures
		8.5.2 Reduction/Elimination of Pstat by Design Measures
		8.5.3 Reduction of Pdyn by Design Measures
			Power Supply (V) Reduction
			Capacitance Reduction
			Reduction of Switching Activity
	8.6 Computing Power Versus Chip Power: A Scaling Perspective
	8.7 Conclusions
	8.8 Exercises
	References
9 Robustness of Nanometer CMOS Designs: Signal Integrity, Variability and Reliability
	9.1 Introduction
	9.2 Clock Generation, Clock Distribution and Critical Timing
		9.2.1 Introduction
		9.2.2 Clock Distribution and Critical Timing Issues
			Single-Phase Clocking
			Clock Skew and Clock Jitter
			Other Timing Problems
			Slack Borrowing and Time Stealing
			Source-Synchronous Timing (Clock Forwarding)
		9.2.3 Clock Generation and Synchronisation in Different (Clock) Domains on a Chip
			On-Chip Multiple-Clock Generation
			Clock-Phase Synchronisation in Multiple Core Environments
	9.3 Signal Integrity
		9.3.1 Cross Talk and Signal Propagation
		9.3.2 Power Integrity, Supply and Ground Bounce
			Backside Power Distribution
		9.3.3 Substrate Bounce
		9.3.4 EMC
		9.3.5 Soft Errors
		9.3.6 Signal Integrity Summary and Trends
	9.4 Variability
		9.4.1 Spatial vs. Time-Based Variations
		9.4.2 Global vs. Local Variations
		9.4.3 Transistor Matching
		9.4.4 From Deterministic to Probabilistic Design
		9.4.5 Can the Variability Problem Be Solved?
	9.5 Reliability
		9.5.1 Punch-Through
		9.5.2 Electromigration
		9.5.3 Hot-Carrier Injection (HCI)
		9.5.4 Bias Temperature Instability (BTI, NBTI and PBTI)
		9.5.5 Latch-Up
		9.5.6 Electrostatic Discharge (ESD)
			ESD Test Models and Procedures
			On-Chip ESD Protection Circuits
		9.5.7 The Use of Guard Rings
		9.5.8 Charge Injection During the Fabrication Process
		9.5.9 Reliability Summary and Trends
	9.6 Design Organisation
	9.7 Conclusions
	9.8 Exercises
	References
10 Testing, Yield, Packaging, Debug and Failure Analysis
	10.1 Introduction
	10.2 Testing
		10.2.1 Basic IC Tests
			Contact Test
			Functional Test
			Delay Fault Test
			Scan Test (Structural Test)
			Iddq and Iddq Test
			Very-Low-Voltage (VLV) Testing
			BIST
			Boundary Scan Test
		10.2.2 Design for Testability
	10.3 Yield
		10.3.1 A Simple Yield Model and Yield Control
		10.3.2 Design for Manufacturability
		10.3.3 Towards Chiplet Design to Reduce ManufacturingCosts
		10.3.4 Redundancy in Logic
	10.4 Packaging
		10.4.1 Introduction
		10.4.2 Package Categories
		10.4.3 Packaging Process Flow
			Backgrinding and Sawing
			Packaging
		10.4.4 Electrical Aspects of Packaging
		10.4.5 Thermal Aspects of Packaging
		10.4.6 Reliability Aspects of Packaging
		10.4.7 Future Trends in Packaging Technology
		10.4.8 System on a Chip (SoC) Versus System in a Package (SiP)
		10.4.9 Quality and Reliability of Packaged Dies
			Quality
			Reliability
		10.4.10 Conclusions
	10.5 Potential First Silicon Problems
		10.5.1 Problems with Testing
		10.5.2 Problems Caused by Marginal or Out-of-Specification Processing
			Gate Oxide Thickness
			Polysilicon Width
			Threshold Voltage
			Substrate (p-Well) and/or n-Well Dope
		10.5.3 Problems Caused by Marginal Design
	10.6 First-Silicon Debug and Failure Analysis
		10.6.1 Introduction
		10.6.2 Iddq and ΔIddq Testing
		10.6.3 Traditional Debug, Diagnosis and Failure Analysis (FA) Techniques
			Diagnosis via Shmoo Plots
			Diagnosis via Probing
			Diagnosis by Photon Emission Microscopy (PEM)
		10.6.4 More Recent Debug and Failure Analysis Techniques
			Time-Resolved Photoemission Microscopy (TR-PEM)
			Scanning Optical Beam (SOM) Techniques (or Laser Signal Injection Microscopy [LSIM])
			Scanning Electron Beam Microscopy (SEM) Techniques
		10.6.5 Observing the Failure
		10.6.6 Circuit Editing Techniques
		10.6.7 Design for Debug and Design for Failure Analysis
	10.7 Conclusions
	10.8 Exercises
	References
11 Effects of Scaling on MOS IC Design and Consequences for the Roadmap
	11.1 Introduction
	11.2 Transistor Scaling Effects
	11.3 Interconnection Scaling Effects
	11.4 Scaling Consequences for Overall Chip Performance and Robustness
	11.5 Potential Limitations of the Pace of Scaling
	11.6 Conclusions
	11.7 Exercises
	References
Index