Modern Receiver Front-Ends: Systems, Circuits, and Integration

MODERN RECEIVER FRONT-ENDS......Page 4
CONTENTS......Page 8
Preface......Page 14
Acknowledgments......Page 16
1 INTRODUCTION......Page 18
1.1 Current State of the Art......Page 20
2.1 Frequency Planning......Page 24
2.1.1 Blockers......Page 25
2.1.3 Transmitter Leakage......Page 27
2.1.4 LO Leakage and Interference......Page 28
2.1.6 Half IF......Page 30
2.2 Link Budget Analysis......Page 31
2.2.1 Linearity......Page 32
2.2.2 Noise......Page 33
2.2.3 Signal-to-Noise Ratio......Page 36
2.2.4 Receiver Gain......Page 37
2.3 Propagation Effects......Page 38
2.3.1 Path Loss......Page 39
2.3.2 Multipath and Fading......Page 40
2.3.5 Coding......Page 41
2.5 Conclusion......Page 42
3 REVIEW OF RECEIVER ARCHITECTURES......Page 44
3.1 Heterodyne Receivers......Page 45
3.2 Image Reject Receivers......Page 47
3.2.1 Hartley Architecture......Page 48
3.3 Zero IF Receivers......Page 49
3.5 Issues in Direct Conversion Receivers......Page 51
3.5.3 Phase and Amplitude Imbalance......Page 55
3.5.4 DC Offset......Page 56
3.5.5 Intermodulations......Page 58
3.7 Conclusion......Page 60
4 SILICON-BASED RECEIVER DESIGN......Page 64
4.1.2 Basics of OFDM......Page 65
4.1.3 System Architectures......Page 67
4.1.4 System Calculations......Page 69
4.2.1 SiGe BiCMOS Process Technology......Page 71
4.2.2 LNA......Page 72
4.2.3 Mixer......Page 74
4.3 Receiver Design Steps......Page 78
4.3.3 Scattering Parameters......Page 79
4.3.4 Small-Signal Performance......Page 80
4.3.6 Noise Performance......Page 81
4.3.7 Linearity Performance......Page 82
4.3.10 50-W and Non-50-W Receivers......Page 85
4.4 Layout Considerations......Page 86
4.5 Characterization of Receiver Front-Ends......Page 87
4.5.4 Conversion Gain Test......Page 88
4.5.5 Linearity Test......Page 90
4.5.8 DC Offset......Page 91
4.6 Measurement Results and Discussions......Page 93
4.6.2 Comments on I/Q Imbalance......Page 96
4.7 Conclusion......Page 97
5 SUBHARMONIC RECEIVER DESIGNS......Page 100
5.1 Illustration of Subharmonic Techniques......Page 101
5.2 Mixing Using Antisymmetric I–V Characteristics......Page 102
5.3 Impact of Mismatch Effects......Page 106
5.4.1 Intrinsic DC Offset Cancellation......Page 109
5.4.2 Extrinsic DC Offset Cancellation......Page 110
5.5 Experimental Verification of DC Offset......Page 111
5.6 Waveform Shaping Before Mixing......Page 115
5.6.1 Theory and Analysis......Page 118
5.6.2 Experimental Verification on GaAs MESFET APDP......Page 119
5.6.3 Implementation in Silicon......Page 123
5.7 Design Steps for APDP-Based Receivers......Page 126
5.8 Architectural Illustration......Page 128
5.9.1 Integrated Direct Conversion Receiver MMIC’s......Page 129
5.9.2 Receiver Blocks......Page 130
5.9.3 Additional Receiver Blocks......Page 138
5.10 Reconfigurable Multiband Subharmonic Front-Ends......Page 141
5.11 Conclusion......Page 142
6 ACTIVE SUBHARMONIC RECEIVER DESIGNS......Page 144
6.1.1 Description and Principles......Page 145
6.1.2 Subharmonic Receiver Architecture......Page 148
6.2.1 Active Mixer......Page 149
6.2.2 Receiver Architecture......Page 151
6.3 Extension to Higher-Order LO Subharmonics......Page 154
6.4 Multiple Phase Signal Generation from Oscillators......Page 156
6.5 Future Direction and Conclusion......Page 157
7 DESIGN AND INTEGRATION OF PASSIVE COMPONENTS......Page 160
7.1 System on Package (SoP)......Page 161
7.1.1 Multilayer Bandpass Filter......Page 163
7.1.2 Multilayer Balun Structure......Page 165
7.1.4 Fully Integrated SoP Module......Page 166
7.2 On-Chip Inductors......Page 169
7.2.1 Inductor Modeling......Page 170
7.2.2 Inductor Parameters......Page 174
7.2.3 Application in Circuits......Page 175
7.3 Capacitors......Page 176
7.4 Differentially Driven Inductors......Page 180
7.5.1 Electrical Parameters......Page 183
7.5.3 Electrical Models......Page 185
7.5.4 Frequency Response of Transformers......Page 189
7.5.5 Step-Up/Step-Down Transformers and Circuit Applications......Page 193
7.6 On-Chip Filters......Page 194
7.6.2 Active Filters......Page 196
7.7 On-Wafer Antennas......Page 202
7.8 Wafer-Level Packaging......Page 204
7.9 Conclusion......Page 205
8.1.1 I/O Counts......Page 208
8.1.2 Cross-Talk......Page 209
8.2 IC Floor Plan......Page 210
8.2.1 Signal Flow and Substrate Coupling......Page 211
8.2.2 Grounding......Page 213
8.2.3 Isolation......Page 214
8.3 Packaging Considerations......Page 215
8.3.1 Package Modeling......Page 216
8.4 Conclusion......Page 217
9.1 CMOS Cellphones......Page 220
9.2 Multiband, Multimode Wireless Solutions......Page 221
9.3 60 GHz Subsystems in Silicon!......Page 222
9.4 Interchip Communications......Page 223
9.5 Ultrawideband Communication Technology......Page 227
9.6 Diversity Techniques......Page 228
9.7 Conclusion......Page 230
Index......Page 234