Modern Processor Design: Fundamentals of Superscalar Processors

About the Authors
Preface
1. Processor Design
....1.1 The Evolution of Microprocessors
....1.2 Instruction Set Processor Design
........1.2.1 Digital Systems Design
........1.2.2 Architecture, Implementation, and Realization
........1.2.3 Instruction Set Architecture
........1.2.4 Dynamic-Static Interface
....1.3 Principles of Processor Performance
........1.3.1 Processor Performance Equation
........1.3.2 Processor Performance Optimizations
........1.3.3 Performance Evaluation Method
....1.4 Instruction-Level Parallel Processing
........1.4.1 From Scalar to Superscalar
........1.4.2 Limits of Instruction-Level Parallelism
........1.4.3 Machines for Instruction-Level Parallelism
....1.5 Summary
2. Pipelined Processors
....2.1 Pipelining Fundamentals
........2.1.1 Pipelined Design
........2.1.2 Arithmetic Pipeline Example
........2.1.3 Pipelining Idealism
........2.1.4 Instruction Pipelining
....2.2 Pipelined Processor Design
........2.2.1 Balancing Pipeline Stages
........2.2.2 Unifying Instruction Types
........2.2.3 Minimizing Pipeline Stalls
........2.2.4 Commercial Pipelined Processors
....2.3 Deeply Pipelined Processors
....2.4 Summary
3. Memory and I/O Systems
....3.1 Introduction
....3.2 Computer System Overview
....3.3 Key Concepts: Latency and Bandwidth
....3.4 Memory Hierarchy
........3.4.1 Components of a Modern Memory Hierarchy
........3.4.2 Temporal and Spatial Locality
........3.4.3 Caching and Cache Memories
........3.4.4 Main Memory
....3.5 Virtual Memory Systems
........3.5.1 Demand Paging
........3.5.2 Memory Protection
........3.5.3 Page Table Architectures
....3.6 Memory Hierarchy Implementation
....3.7 Input/Output Systems
........3.7.1 Types of I/O Devices
........3.7.2 Computer System Busses
........3.7.3 Communication with I/O Devices
........3.7.4 Interaction of I/O Devices and Memory Hierarchy
....3.8 Summary
4. Superscalar Organization
....4.1 Limitations of Scalar Pipelines
........4.1.1 Upper Bound on Scalar Pipeline Throughput
........4.1.2 Inefficient Unification into a Single Pipeline
........4.1.3 Performance Lost Due to a Rigid Pipeline
....4.2 From Scalar to Superscalar Pipelines
........4.2.1 Parallel Pipelines
........4.2.2 Diversified Pipelines
........4.2.3 Dynamic Pipelines
....4.3 Superscalar Pipeline Overview
........4.3.1 Instruction Fetching
........4.3.2 Instruction Decoding
........4.3.3 Instruction Dispatching
........4.3.4 Instruction Execution
........4.3.5 Instruction Completion and Retiring
....4.4 Summary
5. Superscalar Techniques
....5.1 Instruction Flow Techniques
........5.1.1 Program Control Flow and Control Dependences
........5.1.2 Performance Degradation Due to Branches
........5.1.3 Branch Prediction Techniques
........5.1.4 Branch Misprediction Recovery
........5.1.5 Advanced Branch Prediction Techniques
........5.1.6 Other Instruction Flow Techniques
....5.2 Register Data Flow Techniques
........5.2.1 Register Reuse and False Data Dependences
........5.2.2 Register Renaming Techniques
........5.2.3 True Data Dependences and the Data Flow Limit
........5.2.4 The Classic Tomasulo Algorithm
........5.2.5 Dynamic Execution Core 
........5.2.6 Reservation Stations and Reorder Buffer 
........5.2.7 Dynamic Instruction Scheduler 
........5.2.8 Other Register Data Flow Techniques 
....5.3 Memory Data Flow Techniques 
........5.3.1 Memory Accessing Instructions 
........5.3.2 Ordering of Memory Accesses
........5.3.3 Load Bypassing and Load Forwarding
........5.3.4 Other Memory Data Flow Techniques
....5.4 Summary
6. The PowerPC 620
....6.1 Introduction
....6.2 Experimental Framework
....6.3 Instruction Fetching
........6.3.1 Branch Prediction
........6.3.2 Fetching and Speculation
....6.4 Instruction Dispatching
........6.4.1 Instruction Buffer
........6.4.2 Dispatch Stalls
........6.4.3 Dispatch Effectiveness
....6.5 Instruction Execution
........6.5.1 Issue Stalls
........6.5.2 Execution Parallelism
........6.5.3 Execution Latency
....6.6 Instruction Completion
........6.6.1 Completion Parallelism
........6.6.2 Cache Effects
....6.7 Conclusions and Observations
....6.8 Bridging to the IBM POWER3 and POWER4
....6.9 Summary
7. Intel\'s P6 Microarchitecture
....7.1 Introduction
........7.1.1 Basics of the P6 Microarchitecture
....7.2 Pipelining
........7.2.1 In-Order Front-End Pipeline
........7.2.2 Out-of-Order Core Pipeline
........7.2.3 Retirement Pipeline
....7.3 The In-Order Front End
........7.3.1 Instruction Cache and ITLB
........7.3.2 Branch Prediction
........7.3.3 Instruction Decoder
........7.3.4 Register Alias Table
........7.3.5 Allocator
....7.4 The Out-of-Order Core
........7.4.1 Reservation Station
....7.5 Retirement
........7.5.1 The Reorder Buffer
....7.6 Memory Subsystem
........7.6.1 Memory Access Ordering
........7.6.2 Load Memory Operations
........7.6.3 Basic Store Memory Operations
........7.6.4 Deferring Memory Operations
........7.6.5 Page Faults
....7.7 Summary
....7.8 Acknowledgments
8. Survey of Superscalar Processors
....8.1 Development of Superscalar Processors
........8.1.1 Early Advances in Uniprocessor Parallelism: The IBM Stretch
........8.1.2 First Superscalar Design: The IBM Advanced Computer System
........8.1.3 Instruction-Level Parallelism Studies
........8.1.4 By-Products of DAE: The First Multiple-Decoding Implementations
........8.1.5 IBM Cheetah, Panther, and America
........8.1.6 Decoupled Microarchitectures
........8.1.7 Other Efforts in the 1980s
........8.1.8 Wide Acceptance of Superscalar
....8.2 A Classification of Recent Designs
........8.2.1 RISC and CISC Retrofits
........8.2.2 Speed Demons: Emphasis on Clock Cycle Time
........8.2.3 Brainiacs: Emphasis on IPC
....8.3 Processor Descriptions
........8.3.1 Compaq / DEC Alpha
........8.3.2 Hewlett-Packard PA-RISC Version 1.0
........8.3.3 Hewlett-Packard PA-RISC Version 2.0
........8.3.4 IBM POWER
........8.3.5 Intel i960
........8.3.6 Intel IA32—Native Approaches
........8.3.7 Intel IA32—Decoupled Approaches
........8.3.8 x86-64
........8.3.9 MIPS
........8.3.10 Motorola
........8.3.11 PowerPC—32-bit Architecture
........8.3.12 PowerPC—64-bit Architecture
........8.3.13 PowerPC-AS
........8.3.14 SPARC Version 8
........8.3.15 SPARC Version 9
....8.4 Verification of Superscalar Processors
....8.5 Acknowledgments
9. Advanced Instruction Flow Techniques
....9.1 Introduction
....9.2 Static Branch Prediction Techniques
........9.2.1 Single-Direction Prediction
........9.2.2 Backwards Taken/Forwards Not-Taken
........9.2.3 Ball/Larus Heuristics
........9.2.4 Profiling
....9.3 Dynamic Branch Prediction Techniques
........9.3.1 Basic Algorithms
........9.3.2 Interference-Reducing Predictors
........9.3.3 Predicting with Alternative Contexts
....9.4 Hybrid Branch Predictors
........9.4.1 The Tournament Predictor
........9.4.2 Static Predictor Selection
........9.4.3 Branch Classification
........9.4.4 The Multihybrid Predictor
........9.4.5 Prediction Fusion
....9.5 Other Instruction Flow Issues and Techniques
........9.5.1 T arget Prediction
........9.5.2 Branch Confidence Prediction
........9.5.3 High-Bandwidth Fetch Mechanisms
........9.5.4 High-Frequency Fetch Mechanisms
....9.6 Summary
10. Advanced Register Data Flow Techniques
....10.1 Introduction
........10.2 Value Locality and Redundant Execution
........10.2.1 Causes of Value Locality
........10.2.2 Quantifying Value Locality
....10.3 Exploiting Value Locality without Speculation
........10.3.1 Memoization
........10.3.2 Instruction Reuse
........10.3.3 Basic Block and Trace Reuse
........10.3.4 Data Flow Region Reuse
........10.3.5 Concluding Remarks
....10.4 Exploiting Value Locality with Speculation
........10.4.1 The Weak Dependence Model
........10.4.2 Value Prediction
........10.4.3 The Value Prediction Unit
........10.4.4 Speculative Execution Using Predicted Values
........10.4.5 Performance of Value Prediction
........10.4.6 Concluding Remarks
....10.5 Summary
11. Executing Multiple Threads
....11.1 Introduction
....11.2 Synchronizing Shared-Memory Threads
....11.3 Introduction to Multiprocessor Systems
........11.3.1 Fully Shared Memory, Unit Latency, and Lack of Contention
........11.3.2 Instantaneous Propagation of Writes
........11.3.3 Coherent Shared Memory
........11.3.4 Implementing Cache Coherence
........11.3.5 Multilevel Caches, Inclusion, and Virtual Memory
........11.3.6 Memory Consistency
........11.3.7 The Coherent Memory Interface
........11.3.8 Concluding Remarks
....11.4 Explicitly Multithreaded Processors
........11.4.1 Chip Multiprocessors
........11.4.2 Fine-Grained Multithreading
........11.4.3 Coarse-Grained Multithreading
........11.4.4 Simultaneous Multithreading
....11.5 Implicitly Multithreaded Processors
........11.5.1 Resolving Control Dependences
........11.5.2 Resolving Register Data Dependences
........11.5.3 Resolving Memory Data Dependences
........11.5.4 Concluding Remarks
....11.6 Executing the Same Thread
........11.6.1 Fault Detection
........11.6.2 Prefetching
........11.6.3 Branch Resolution
........11.6.4 Concluding Remarks
....11.7 Summary
Index