MIPI Specification for I3C Version 1.0

Contents......Page 3
Figures......Page 7
Tables......Page 10
Release History......Page 13
1 Introduction......Page 15
1.2 I3C Purpose......Page 16
1.3 I3C Key Features......Page 17
2.2 Definitions......Page 19
2.4 Acronyms......Page 22
3.2 Informative References......Page 24
4 Technical Overview (Informative)......Page 25
4.1 I3C Fundamental Principles......Page 26
4.2 I3C Master and Slave Devices......Page 29
4.2.1 I3C Master Device......Page 30
4.2.1.1 I3C Master Device Roles......Page 31
4.2.2 I3C Slave Device......Page 32
4.2.2.1 I3C Slave Device Roles......Page 33
5.1 Single Data Rate (SDR) Mode......Page 34
5.1.1.1 I3C Device Characteristics......Page 35
5.1.1.2 I3C Characteristics Registers......Page 38
5.1.1.2.1 Bus Characteristics Register (BCR)......Page 39
5.1.1.2.3 Legacy Virtual Register (LVR)......Page 40
5.1.2 Bus Communication......Page 41
5.1.2.1 Role of I3C Slave......Page 42
5.1.2.2 I3C Address Header......Page 43
5.1.2.2.2 I3C Address Arbitration Optimization......Page 44
5.1.2.2.3 Consequence of Master Starting a Frame with an I3C Slave Address......Page 45
5.1.2.2.5 I3C Slave Address Restrictions......Page 46
5.1.2.3.1 Transition from Address ACK to SDR Master Write Data......Page 48
5.1.2.3.3 Ninth Bit of SDR Slave Returned (Read) Data as End-of-Data......Page 49
5.1.2.4.1 Use of Duty Cycle to Achieve Lower Effective Speed in a Mixed Fast Bus......Page 50
5.1.2.5 Master Clock Stalling......Page 51
5.1.2.5.1 I3C/I2C Transfer, ACK/NACK Phase......Page 52
5.1.2.5.3 I3C Read Transfer, Transition Bit......Page 53
5.1.2.5.4 Dynamic Address Assignment, First Bit of Assigned Address......Page 56
5.1.3.1 Open Drain Pull-Up and High-Keeper......Page 57
5.1.3.5 Activity States......Page 58
5.1.4 Bus Initialization and Dynamic Address Assignment Mode......Page 59
5.1.4.2 Bus Initialization Sequence with Dynamic Address Assignment......Page 60
5.1.4.3 Provisional ID Collision Detection and Correction......Page 63
5.1.5 Hot-Join Mechanism......Page 64
5.1.5.1 Failsafe Device Pads......Page 65
5.1.6.2 I3C Slave Interrupt Request......Page 66
5.1.6.3 I3C Secondary Master Requests to be Current Master......Page 67
5.1.6.4 I3C Main Master Initiating a Transaction......Page 68
5.1.7.2 Bus Management Procedures......Page 69
5.1.7.5 Hot-Join Management......Page 70
5.1.8.1 General Principles......Page 71
5.1.8.2 Synchronous Systems and Events......Page 72
5.1.8.3 Asynchronous Systems and Events......Page 75
5.1.8.3.1 Async Mode 0: Asynchronous Basic Mode......Page 80
5.1.8.3.2 Async Mode 1: Asynchronous Advanced Mode......Page 82
5.1.8.3.3 Async Mode 2: Async High-Precision Low-Power Mode......Page 84
5.1.8.3.4 Async Mode 3: Async High-Precision Triggereable Mode......Page 87
5.1.9.1 CCC Command Format......Page 90
5.1.9.2.1 End of a CCC Command......Page 91
5.1.9.2.3 Retry Model for Direct GET CCC Commands......Page 92
5.1.9.3 CCC Command Definitions......Page 94
5.1.9.3.1 Enable/Disable Slave Events Command (ENEC/DISEC)......Page 98
5.1.9.3.3 Reset Dynamic Address Assignment (RSTDAA)......Page 99
5.1.9.3.5 Set/Get Max Write Length (SETMWL/GETMWL)......Page 100
5.1.9.3.7 Define List of Slaves (DEFSLVS)......Page 101
5.1.9.3.9 Enter HDR Mode 0–7 (ENTHDR0–ENTHDR7)......Page 102
5.1.9.3.10 Set Dynamic Address from Static Address (SETDASA)......Page 103
5.1.9.3.14 Get Device Characteristics Register (GETDCR)......Page 104
5.1.9.3.15 Get Device Status (GETSTATUS)......Page 105
5.1.9.3.16 Get Accept Mastership (GETACCMST)......Page 106
5.1.9.3.18 Get Max Data Speed (GETMXDS)......Page 107
5.1.9.3.20 Set Exchange Timing Information (SETXTIME)......Page 109
5.1.9.3.21 Get Exchange Timing Support Information (GETXTIME)......Page 111
5.1.10.1 SDR Error Detection and Recovery Methods for I3C Slave Devices......Page 112
5.1.10.1.4 Error Type S3......Page 113
5.1.10.2 SDR Error Detection and Recovery Methods for I3C Master Devices......Page 114
5.1.10.2.3 Error Type M2......Page 115
5.1.10.2.4 Master Error Detection and Escalation Handling......Page 116
5.2 High Data Rate (HDR) Modes......Page 117
5.2.1.1 HDR Exit Pattern......Page 118
5.2.1.3 HDR Exit Pattern Detector......Page 119
5.2.1.4 HDR Restart and Exit Pattern Detector......Page 121
5.2.1.5 Compatibility of HDR Pattern Detection and Ternary Modes......Page 123
5.2.2 HDR Double Data Rate Mode (HDR-DDR)......Page 124
5.2.2.1 HDR-DDR Overview......Page 127
5.2.2.2 HDR-DDR Command Coding......Page 131
5.2.2.3.1 Command to Read Data from Slave......Page 133
5.2.2.3.3 Master Termination of a Read Command Message......Page 134
5.2.2.4 HDR-DDR Error Detection......Page 135
5.2.2.5 HDR-DDR CRC5 Algorithm......Page 136
5.2.3.1.1 Ternary Signaling......Page 137
5.2.3.1.2 Ternary Coding Protocol......Page 138
5.2.3.2 HDR Ternary Command Coding......Page 145
5.2.3.3 HDR Ternary Bus Turnaround......Page 147
5.2.3.4 HDR Ternary Error Detection......Page 148
6.1 DC I/O Characteristics......Page 149
6.2 Timing Specification......Page 153
A.1 I3C CCC Transfers......Page 173
A.2 I3C Private Write and Read Transfers......Page 174
A.3 Legacy I2C Write and Read Transfers on the I3C Bus......Page 176
A.4 Dynamic Address and Enter HDR......Page 177
B.1 Error Types in I3C CCC Transfers......Page 179
B.2 Error Types in I3C Private Read and Write Transfers......Page 180
B.3 Error Types in Dynamic Address Arbitration......Page 182
Annex C I3C Master FSMs......Page 183
Annex D Typical I3C Protocol Communications......Page 191
Participants......Page 197