Low-power electronics design

Part I Technologies and Devices......Page 1
Contents......Page 0
1.1 Introduction......Page 2
1.2.2 Reused Concepts for Low Power......Page 3
1.3 Transistors and Integrated Circuits......Page 4
1.3.1 Invention of the Transistor......Page 5
1.3.3 MOS Transistors......Page 6
1.3.4 Early Microprocessors......Page 7
1.3.5 RISC Machines......Page 8
1.4.1 First Electronic Wristwatch......Page 9
1.5 The Dramatic Increase in Power......Page 11
1.5.2 Low- Power Design Techniques......Page 12
1.6 Conclusion......Page 14
References......Page 15
2.1 Introduction......Page 17
2.2.3 SOI Technologies......Page 18
2.3.1 Subthreshold Leakage and Voltage Limits......Page 19
2.3.3 Bulk CMOS Design Solutions for Subthreshold Leakage......Page 20
2.3.4 SOI CMOS Design Solutions for Subthreshold Leakage......Page 21
2.4.1 Tunneling Effects......Page 22
2.4.3 Design Issues and Possible Solutions......Page 23
2.4.4 High- K Materials and Other Device Options......Page 24
2.5.1 Dopant Fluctuation......Page 25
2.6.1 Poly Depletion......Page 26
2.6.3 Circuit Dynamic Performances......Page 27
2.7.1 Strained Silicon......Page 28
2.7.2 Multiple Gate Devices......Page 29
References......Page 30
3.2 ILEAK Components of MOSFET Devices......Page 33
3.2.1 Gate Tunneling Currents......Page 35
3.2.2 Subthreshold Leakage Currents......Page 38
3.2.3 Gate- Induced Drain Leakage Currents......Page 41
3.2.4 Junction Leakage Currents......Page 42
3.3.2 Short- Channel Effects......Page 43
3.3.3 Gate- Tunneling Currents......Page 44
3.4 Circuit Level......Page 45
3.5 Conclusions......Page 48
References......Page 49
4.1 Introduction......Page 52
4.2.2 Silicon MOSFETs in the Nanometer Regime......Page 53
4.3 Ultimate Limits of the Silicon MOSFET......Page 55
4.5 Beyond the Silicon MOSFET......Page 56
4.5.1 Carbon Nanotube Transistors......Page 57
4.5.2 Organic Molecular Transistors......Page 58
4.6.1 Single- Electron Transistors......Page 59
4.7 From Microelectronics to Nanoelectronics......Page 60
References......Page 61
5.1 The Interconnect Problem......Page 64
5.1.1 Analysis of Electrical Interconnect Performance......Page 65
5.1.3.2 Broadcast ( 1- n) Links......Page 66
5.2.1.1 Materials......Page 67
5.2.1.2 Hybrid or Monolithic......Page 68
5.3.1 Waveguides......Page 69
5.3.3 Photonic Crystals......Page 71
5.4.2 Detectors......Page 72
5.5.2 Receiver Circuits......Page 73
5.6 Bonding Issues......Page 75
5.7 Link Performance ( Comparison of Optical and Electrical Systems)......Page 77
5.8 Research Directions......Page 79
5.8.1 Network Links......Page 80
References......Page 81
Part II Low-Power Circuits......Page 84
6.1 Introduction......Page 85
6.2.2 Fast Input Range......Page 86
6.2.4 Extension to Gates......Page 87
6.3.1 Metric for the Transition Time......Page 88
6.3.2 Metric for the Process......Page 90
6.3.4 Metric for the Delay......Page 91
6.3.4 Metric for the Short- Circuit Power Dissipation......Page 92
6.4.1 Continuous Representation of Standard Cell Performance......Page 94
6.4.3 Validation......Page 95
6.5.1 Rule for Slope Control......Page 97
6.5.2 Application......Page 98
6.5.3 Validation......Page 99
References......Page 100
7.2.1 Static CMOS Logic......Page 102
7.2.2 Branch- Based Logic......Page 103
7.2.3 Transmission Gates......Page 104
7.2.4 N- Pass Logic......Page 105
7.2.5 Dynamic Precharged Logic......Page 106
7.2.7 Double- Edge Triggered Flip- Flops......Page 107
7.3 Low- Power and Standard Cell Libraries......Page 108
7.3.2 Latch- Based Designs......Page 109
7.3.4 Complex Gate Decomposition......Page 110
7.3.5 Standard Cell Libraries......Page 111
7.3.6 Static Power......Page 112
7.4 Logic Styles for Specific Applications......Page 114
7.4.1 Library Cells for Self- Timed Design......Page 115
7.4.2 Library Cells for Cryptographic Applications......Page 116
7.5 Conclusion......Page 117
References......Page 118
8.1 Introduction......Page 120
8.2.1 TSPC Latches and Flip- Flops......Page 121
8.2.2 Differential Single- Clock Latches and Flip- Flops......Page 124
8.2.3 Power- Delay Comparison......Page 126
8.3.1 TSPC Pipeline......Page 127
8.3.3 Clock- and- Data Precharged Circuit Technique......Page 128
8.3.4 United Connection Rules of TSPC and CDPD Stages......Page 130
8.4.1 Dividers and Ripple Counters......Page 131
8.4.2 Synchronous Counter......Page 132
8.4.3 Nonbinary Divider and Prescaler......Page 134
8.4.4 Adder and Accumulator......Page 135
8.4.5 Bit- Serial Comparator and Sorter......Page 136
8.6 Conclusion......Page 137
References......Page 138
9.1 Introduction......Page 140
9.2.1 1- Bit Addition Cells......Page 141
9.2.2 Sequential Adder......Page 142
9.2.4 Carry Select Adder......Page 143
9.2.6 Logarithmic Adders......Page 144
9.2.8 Redundant Adders......Page 145
9.3 Multiplication......Page 146
9.3.1 Partial Products Generation......Page 147
9.3.2 Reduction Trees......Page 148
9.3.3 Final Addition......Page 149
9.3.6 Square......Page 150
9.4.1 Division and Square Root......Page 151
9.4.3 Floating- Point Arithmetic......Page 152
References......Page 153
10.2 Dynamic Power Consumption Component......Page 155
10.3 Circuit Parallelization......Page 157
10.3.1 Memory Parallelization......Page 158
10.3.3 Serial- Parallel Converter......Page 160
10.3.5 Double- Edge Triggered Flip- Flop......Page 161
10.4.1 Multiple Voltages Techniques......Page 163
10.4.2 Low Voltage Swing......Page 166
10.5.1 Precomputation......Page 169
10.5.2 Retiming......Page 170
10.6.1 Path Balancing......Page 171
10.6.3 Technology Mapping......Page 172
References......Page 173
11.1 Introduction......Page 176
11.2.2 RTL Coding Applicability to Power Reduction......Page 177
11.2.5 Explicit- State Encoding......Page 178
11.3.1 Gate- Level Control......Page 179
11.4.1 Flip- Flop- Based Design......Page 180
11.4.2.1 Timing Issues......Page 184
11.4.3 Latch- Based Design......Page 185
11.4.4 Issues in Latch- Based Design......Page 187
11.5.1 Gated- Clock FSM......Page 188
11.5.3 FSM Partitioning......Page 189
11.6.1 Precomputation Design Techniques......Page 190
11.6.3 Control- Signal Gating Design Techniques......Page 192
11.7.1 Bus Invert Encoding......Page 194
11.8 Conclusion......Page 195
References......Page 196
12.1.1 Clock Distribution......Page 197
12.2 Clocking Considerations in Sequential Systems......Page 198
12.2.1 Clocked Storage Elements......Page 199
12.2.1.2 Setup and Hold Time Properties......Page 200
12.2.2 Time Borrowing and Absorption of Clock Uncertainties......Page 201
12.4 Globally Asynchronous Locally Synchronous Systems......Page 204
References......Page 206
13.1 Introduction......Page 208
13.2.1 Subthreshold Leakage......Page 209
13.2.3 Source/ Substrate and Drain/ Substrate P- N Junction Leakage......Page 210
13.4.1 Dual Threshold CMOS......Page 211
13.4.2 Multiple Supply Voltage......Page 212
13.5.1 Leakage Control Using Transistor Stacks ( Self- Reverse Bias)......Page 213
13.5.2 Sleep Transistor......Page 215
13.5.3 Variable Threshold CMOS ( VTCMOS)......Page 216
13.6.2 Dynamic Vth Scaling (DVTS)......Page 217
13.7 Circuit Techniques to Reduce Leakage in Cache Memories......Page 219
References......Page 222
14.1 Introduction......Page 225
14.2.1 General......Page 226
14.2.2 Interconnect Delays......Page 227
14.2.3 Wires with Repeaters......Page 228
14.3.1 Basics......Page 229
14.3.2 Power Consumption Related to Drivers and Repeaters......Page 230
14.3.3 Power Related to Precharged Buses......Page 231
14.4.2 Reduced Voltage Swing......Page 232
14.4.3 Reduced Interconnect Activity......Page 233
14.4.4 Power Savings in Drivers and Repeaters......Page 234
14.4.5 Off- Chip Interconnect......Page 235
14.6 Conclusion......Page 237
References......Page 238
15.2 The Adiabatic- Charging Principle......Page 240
15.3.1 Adiabatic Logic......Page 242
15.3.2 Adiabatic Buffering......Page 245
15.3.3 Adiabatic Power Supplies......Page 249
15.4 Conclusion......Page 252
References......Page 253
16.1 Introduction......Page 255
16.2 MOS Model in Weak Inversion and Basic Assumptions......Page 256
16.3 Static CMOS Inverter......Page 257
16.4.2 Currents and Charges......Page 259
16.5.1 Definition and Delay Time......Page 260
16.5.2 Currents and Charges......Page 261
16.5.4 Power- Delay Product......Page 262
16.5.5 Minimum Delay Time in Weak Inversion......Page 264
16.6.2 Required Voltage Swing......Page 265
16.6.3 Degeneration of Logic States......Page 266
16.7 Extension to Logic Gates and Numerical Examples......Page 267
16.8.2 Low- Threshold and Threshold Adjustment......Page 268
16.8.3 Symmetry and Matching......Page 269
16.8.5 System Architecture and Applications......Page 270
References......Page 271
17.1 Introduction......Page 273
17.2 Signal Integrity......Page 275
17.2.1 Cross Talk and Signal Propagation......Page 276
17.2.2 Supply and Ground Bounce......Page 278
17.2.3 Substrate Bounce......Page 280
17.2.4 EMC......Page 281
17.2.5 Soft Errors......Page 282
17.2.7 Statistical Timing Analysis......Page 283
17.2.8 Signal Integrity Summary and Trends......Page 284
17.3.1 Electromigration......Page 285
17.3.2 Hot- Carrier Degradation......Page 287
17.3.3 Negative Bias Temperature Instability ( NBTI)......Page 288
17.3.4 Latch- Up......Page 289
17.3.5.1 ESD Test Models and Procedures......Page 291
17.3.5.2 On- Chip ESD Protection Circuits......Page 292
17.4 Conclusion......Page 293
17.5 Acknowledgment......Page 295
References......Page 296
Part III Low-Power Processors and Memories......Page 297
18.1 Introduction......Page 299
18.2.1 Active Power and Delay......Page 300
18.3 Process Selection and Rationale......Page 301
18.3.1 Effective Frequency......Page 302
18.4 Leakage Control via Reverse Body Bias......Page 303
18.4.2 Circuit Configuration......Page 304
18.4.4 Regulator Design......Page 306
18.4.6 Measured Results......Page 308
18.5 System Level Performance......Page 309
18.5.1 System Measurement Results......Page 310
18.6 Process, Voltage, and Temperature Variations......Page 311
18.6.1 Process Variation......Page 312
18.6.3 Temperature Variation......Page 313
18.7.2 Microarchitecture Choice Impact......Page 314
18.8.1 Body Bias Control Techniques......Page 315
18.8.2 Adaptive Body Bias and Supply Bias......Page 317
18.9.1 Clock Generation......Page 318
18.9.2 Experimental Results......Page 320
References......Page 321
19.1 Introduction......Page 323
19.2 The Application Driver......Page 324
19.3.1.1 Memory Architectures......Page 326
19.3.2.1 Memory Architecture......Page 329
19.3.2.3 Datapath Support......Page 330
19.3.3 Turbo Decoding......Page 331
19.3.3.1 Datapath Architecture......Page 332
19.4 DSPs as Part of SoCs......Page 333
19.6 Acknowledgments......Page 335
References......Page 336
20.1 Introduction......Page 338
20.2.1 Problem Definition......Page 339
20.2.2.2 Exploiting the Parallelism......Page 340
20.2.2.3 Reducing the Control Overhead......Page 341
20.3.1 Cluster Architecture......Page 342
20.3.2 RDP Architecture......Page 343
20.3.3.1 SCMD Concept......Page 344
20.3.3.3 Software Reconfiguration......Page 345
20.4 Validation Results......Page 346
20.4.1 Implementation of a WCDMA Receiver......Page 347
20.4.3 Performance Comparisons......Page 348
20.6 Acknowledgments......Page 350
References......Page 351
21.1.1 DSP Architectures Evolution......Page 353
21.1.2 Parallelism, Instruction Coding, Scheduling, and Execution......Page 354
21.1.3 High- Performance for Low- Power Systems......Page 355
21.1.4 DSP Performance and Reconfigurability......Page 356
21.2.2 Program Sequencing Unit......Page 357
21.2.5 Host and Debug Unit......Page 359
21.2.7 Pipeline......Page 360
21.2.8 Instruction- Set......Page 361
21.3.1 Address Generation Unit Reconfiguration......Page 363
21.3.2 Data Processing Unit Reconfiguration......Page 364
21.4 Performance Results......Page 366
References......Page 369
22.1 Introduction......Page 371
22.2.1 Datapaths......Page 372
22.2.2 Pipelines......Page 373
22.3 Design Methodologies for Low Power......Page 374
22.4.2 MiniMIPS......Page 376
22.4.3 AMULET1, 2, 3......Page 377
22.4.5 Lutonium......Page 378
22.4.6 MICA......Page 379
22.4.7 ASPRO......Page 381
22.5.1 Introduction......Page 382
22.5.2 Principles of Power Reduction with Operating Systems......Page 383
22.5.4.1 Timing Model for Asynchronous Processor Speed Variation......Page 384
22.5.6.2 Sporadic Task Voltage Scheduling Algorithm......Page 386
22.5.5.3 Periodic Task Voltage Scheduling Algorithm......Page 388
References......Page 389
23.1 Introduction......Page 394
23.2.2 The Transmitter......Page 395
23.2.5 Comparison with a General DSP Processor......Page 396
23.2.6 Classification of Baseband Processors......Page 397
23.3.1 Basic Principles for Low- Power Design......Page 398
23.3.3 Nonprogrammable Low- Power Baseband Processor Architecture......Page 399
23.3.4 Programmable Baseband Processor ( PBP) Architectures......Page 400
23.3.5 PBP Design Challenges......Page 403
23.3.6 Decreasing Supply Voltage......Page 404
23.3.8 System- Level Power Management......Page 405
23.4 Case Study One: Variable Data Length and Computing Precision......Page 406
23.5.3 A New Block Interleaver Implementation......Page 407
23.5.5 Power Issues......Page 408
References......Page 409
24.1 Introduction......Page 411
24.2 Leakage Reduction......Page 412
24.3 Noise Margin and Speed Requirements......Page 414
24.4 Locally Switched Source- Body Bias......Page 415
24.5 Results......Page 417
References......Page 418
25.1 Introduction......Page 420
25.2 Cache Organization......Page 422
25.3.1 Miss Rate......Page 423
25.3.6 Leakage......Page 424
25.4.1 Reducing Cache Access Rate......Page 425
25.4.2.1.1 Word-Line Segmentation......Page 426
25.4.2.1.3 Bit-Line Isolation......Page 427
25.4.2.2.2 Way Prediction......Page 428
25.4.2.2.3 Selective Cache Ways......Page 430
25.4.2.2.4 Selective Cache Sets......Page 431
25.4.2.2.6 Reducing Switching Activity of Tag Checks......Page 432
25.4.2.2.7 Data Compression......Page 434
25.4.4 Leakage Energy Reduction......Page 435
References......Page 437
26.1 Introduction......Page 441
26.2 Memory Partitioning......Page 442
26.2.1 Memory Partitioning for Low Energy......Page 443
26.3 Memory Transfer Optimization......Page 445
26.3.1 Code Compression......Page 446
26.3.2 Data Compression......Page 449
26.4 Conclusions......Page 450
References......Page 451
Part IV Low-Power Systems on Chips......Page 453
27.1 Introduction......Page 454
27.2 Hardware Intensity......Page 455
27.3 Architectural Complexity......Page 458
27.4.1 Frequency- Invariant Formulation......Page 460
27.5 Other Power Performance Metrics......Page 464
27.6 Example: Adding an Execution Bypass......Page 465
27.7 Conclusions......Page 466
References......Page 467
28.1 Introduction......Page 468
28.2 Related Work......Page 469
28.3.2 SoC Architecture Generation......Page 470
28.4.2 OS Library......Page 472
28.4.3.1 Architecture Analyzer......Page 473
28.4.4 Application to Existing OSs......Page 474
28.5 Experiments......Page 475
28.5.2 VDSL Example......Page 476
28.6 Conclusion......Page 479
References......Page 480
29.1 Introduction......Page 481
29.2 Related Work......Page 482
29.3 SW- Controlled Memory Hierarchy Optimization......Page 483
29.3.1 Memory Hierarchy Layer Assignment Techniques......Page 485
29.3.2 Illustration of the MHLA Techniques......Page 486
29.3.4 Relation to Other Steps of the DTSE Design Methodology......Page 487
29.4.1 The QSDPCM Driver......Page 488
29.4.3 The DAB Driver......Page 490
29.5.1 Compiler- Centric Cache Miss Classification......Page 491
24.5.1.3 Block Prefetch Misses......Page 492
24.5.1.7 Data- Layout Conflict Misses......Page 493
24.5.2 Data- Layout Transformations for Conflict Miss Reduction......Page 494
24.5.3 Case Study for Data- Layout Transformations......Page 496
References......Page 497
30.1 Introduction......Page 500
30.2 Micro- Networks: Architectures and Protocols......Page 501
30.2.2 Data Link, Network, and Transport Layers......Page 502
30.2.3 Software Layers......Page 504
30.3.2 Data- Link Layer......Page 505
30.3.3.2 Wormhole Contention- Look- Ahead Algorithm......Page 507
30.3.3.3 Network Power Consumption......Page 508
30.3.3.5 Interconnect Network Power Consumption......Page 510
References......Page 513
31.1.1 Motivation......Page 516
31.1.3.1 Average Power Dissipation......Page 518
31.1.3.3 Integration and Cost......Page 519
31.2.1 Introduction to RF MEMS......Page 520
31.2.2.3 MEMS/ CMOS Codesign......Page 521
31.3.2.1 TRF Envelope Detection......Page 522
31.3.3 Super- Regenerative......Page 523
31.4 Transmitters for Ad Hoc Wireless Sensor Networks......Page 524
31.4.2 Two- Step Transmitter......Page 525
31.4.3 Direct- Modulation Transmitter......Page 526
31.5.1 Low- Current RF Amplification......Page 527
31.5.2 Envelope Detector......Page 529
31.5.4 Nonlinear Power Amplifiers......Page 530
31.5.5 On- Chip References and Bias Circuits......Page 533
31.6 System Integration......Page 534
31.8 Acknowledgments......Page 536
References......Page 537
32.1 Introduction......Page 539
32.2 MANET Routing Protocols......Page 540
32.2.2 Reactive ( On- Demand) Protocols......Page 541
32.2.3 Hybrid Routing Protocols......Page 542
32.3.1 Minimum Power Routing......Page 543
32.3.2 Battery- Cost Lifetime- Aware Routing......Page 545
32.3.3.2 Geography- Informed Energy Conservation for Ad Hoc Routing......Page 548
32.3.3.3 Topology Maintenance for Energy Efficiency in Ad Hoc Networks ( Span)......Page 549
32.3.4.2 Energy- Aware Multicast Routing......Page 550
32.3.4.3 The Neighbor Cost Effect in Multicast Routing......Page 551
32.4.1 Cost Function......Page 553
32.4.3 Route Maintenance......Page 554
32.5.1.1 Lifetime Prediction......Page 555
32.5.2 Route Discovery......Page 557
32.5.3 Route Expiration......Page 558
32.6.2 Simulation Results......Page 559
References......Page 564
33.1.1 Computational Surfaces......Page 566
33.2 Colloidal Computing......Page 569
33.3.1 Driver Application: Beamforming......Page 570
33.5 Simulation Infrastructure......Page 571
33.5.1 Processing Devices......Page 573
33.5.3 Battery Subsystem......Page 576
33.7 Acknowledgments......Page 578
References......Page 579
Part V Embedded Software......Page 580
34.1 Introduction......Page 581
34.2.1 Experimental Setups for Average and Instantaneous Current......Page 582
34.2.3 Example of Statistically Generated Model for Average Power......Page 584
34.3 Instruction- Level Models for Predicting Instantaneous Power......Page 588
34.4 Emerging Applications of Instantaneous Power Prediction: Security......Page 589
34.4.1 Simple Power Analysis......Page 590
34.4.2 Differential Power Analysis......Page 591
References......Page 593
35.2 Why Compilers?......Page 595
35.3.1 Power vs. Energy......Page 597
35.3.2 Power/ Energy vs. Performance......Page 598
35.4.1 Dynamic Voltage and Frequency Scaling......Page 599
35.4.3 Remote Task Mapping......Page 600
References......Page 601
36.1 Introduction......Page 603
36.1.1 Processor Cores in SoC Design......Page 604
36.1.2 SoC Integration and Low- Power Design......Page 605
36.2.1 The Chess/ Checkers Retargetable Tool- Suite......Page 606
36.2.2 Architectural Scope......Page 608
36.2.3 Architectural Exploration......Page 609
36.2.4 Power- Conscious Architectural Design......Page 610
36.3.1 General Characteristics......Page 612
36.3.2 Instruction- Set Architecture......Page 614
36.3.3 Micro- Architecture......Page 615
36.4 An Ultra- Low Power DSP for Audio Coding Applications......Page 616
36.4.2 Architecture......Page 617
36.4.3 Low- Power Techniques......Page 619
36.4.4 Results......Page 620
References......Page 621
37.1 Introduction......Page 623
37.2.1 Input Code......Page 624
37.2.2 Loop Fusion......Page 625
37.2.6 Tiling......Page 626
37.2.9 Tiling as a Loop Transformation......Page 627
37.2.11 Implementation and Tests......Page 628
37.2.14 Conclusion......Page 629
37.3 Exploiting Task- Level and Data- Level Parallelism on the Intel IXP1200......Page 630
37.3.2 Performance Modeling and Evaluation......Page 631
37.3.4 Modeling IXP1200 Architecture......Page 632
37.3.6.2 Per- Packet Time Distribution......Page 633
37.3.6.3 Implementation Results......Page 634
37.3.6.4 Exploring the Implementation Space......Page 635
37.4 Advanced Functional Coverification Using SSDE......Page 636
37.4.1 Coverification Using Our System and Software Design Environment ( SSDE)......Page 637
37.4.4 Overview of Seamless......Page 638
37.4.5 Overview of Specman Elite......Page 639
37.4.6.2 e- Based Executable Test Plan......Page 640
37.4.8 Manual Tests Development......Page 642
37.4.9 Automatic Test Pattern Generation......Page 643
References......Page 644
Part VI CAD Tools for Low Power......Page 647
38.1 Introduction......Page 648
38.1.2.1 Switched Capacity Power......Page 649
38.2.1 Generic Power Estimation and Analysis Flow......Page 650
38.2.2 Low- Power Design Flow......Page 652
38.3.1 Objectives of System- Level Design......Page 653
38.3.2 Analysis of an Implementation Model......Page 655
38.3.3 Analysis of an Execution Model......Page 657
38.4 Algorithmic- Level Power Estimation and Analysis......Page 658
38.4.1 Software Power Analysis......Page 660
38.4.2.1 Target Architecture......Page 662
38.4.2.3 Resource Allocation Binding and Sharing......Page 663
38.4.2.6 Interconnect Power Estimation......Page 665
38.5 ORINOCO: A Tool for Algorithmic- Level Power Estimation......Page 667
References......Page 669
39.1 Introduction......Page 672
39.2.1 Model Granularity......Page 673
39.2.2 Model Parameters......Page 674
39.2.2.1 Activity Parameters......Page 675
39.2.3 Model Semantics......Page 676
39.2.4.1 Model Construction......Page 677
39.2.5.1 Accuracy Metrics......Page 678
39.3 RTL Power Macro- Modeling and Estimation......Page 679
39.3.1 Macro- Modeling Flow......Page 680
39.3.2 Macro- Modeling Example......Page 681
39.3.3 RTL Power Estimation Based on Macro- Modeling......Page 683
39.4 RTL Power Estimation in Real- Life Settings......Page 684
39.4.1 Power Models of Non- Synthetic Operators......Page 685
39.5 Conclusions......Page 686
References......Page 687
40.1 Introduction......Page 690
40.2 Clock Gating......Page 691
40.3 Automated Clock Gating at the Register Level......Page 692
40.3.3 Effect of Clock Skew......Page 693
40.3.5 Physical Clock Gating......Page 694
40.3.6 Testability Concerns......Page 695
40.4 Operand Isolation......Page 696
40.5 Logic Optimization......Page 697
40.5.2 Technology Mapping......Page 698
40.5.4 Algebraic Transformations......Page 699
40.6.1 Multi- Threshold Design......Page 700
40.6.2 Variable Threshold Biasing......Page 701
40.7 Voltage Scaling......Page 702
40.8.2 Internal Power......Page 704
40.8.3 Leakage or Static Power Modeling......Page 705
40.8.4 Scalable Polynomial Power Models ( SPPMs)......Page 706
40.9 Analysis Flows......Page 707
References......Page 708
41.1 Introduction......Page 710
41.2.1 Dynamic Power......Page 711
41.2.2 Static Power......Page 712
41.3.3 Multiple Corner Analysis......Page 713
41.4 Power Optimization......Page 714
41.4.1 Power Management......Page 715
41.4.2 Gate Sizing......Page 717
41.5 Rail Analysis......Page 718
41.5.2 Voltage- Drop- Induced Analysis......Page 719
41.5.5 Partial Grids......Page 721
41.6.1 Grid Synthesis......Page 722
41.7 Conclusion......Page 723
42.1 Introduction......Page 724
42.2.2 Power- Sensitive Design Challenges......Page 725
42.2.3 Feed Forward Design Flow......Page 726
42.3.1 PowerTheater......Page 728
42.3.2 Using PowerTheater......Page 729
42.3.4 PhysicalStudio......Page 732
42.3.4 Using PhysicalStudio......Page 733
42.3.5 CoolTime......Page 735
42.3.6 Using CoolTime......Page 738
42.4.1 High- Level Design......Page 739
References......Page 740
Part VII Battery Cells, Sources of Energy, and Chip Cooling......Page 742
43.1 Introduction......Page 743
43.2 Non- Idealities of Real- Life Battery Cells......Page 744
43.3.1 Peukert Equation......Page 745
43.3.3 Efficiency Factor......Page 746
43.3.5 Discrete Time Model for System- Level Design......Page 747
43.3.5.1 Battery......Page 748
43.3.5.2 DC- DC Converter......Page 749
43.3.5 Discrete Time Model for System- Level Design......Page 750
43.4.1 Battery- Driven Dynamic Power Management......Page 751
43.4.4.2 Closed- Loop Policy......Page 752
43.4.2 Battery- Aware Task Scheduling......Page 753
43.4.3 Supply Voltage Scaling......Page 756
43.5 Multi- Battery Systems......Page 757
43.5.1 The Virtual Parallel vs. Serial Policy......Page 758
43.5.3 Simultaneous Discharge......Page 760
43.7 Conclusions......Page 761
References......Page 762
44.1.2 Energy, Power, and Service Requirements of Next- Generation Portable Equipment......Page 764
44.2.1 Secondary Batteries......Page 765
44.2.2 Primary Batteries......Page 767
44.2.3 Metal- Air Systems......Page 768
44.3.1 Principle......Page 769
44.3.2 Applications......Page 770
44.3.3.1.2 Fuel Cells Developed According to Microfabrication Techniques......Page 772
44.3.3.2.1 Overall Sizing......Page 775
44.3.3.2.3.2 Pressurized Hydrogen......Page 776
44.3.3.2.3.5 Steam Reforming......Page 777
44.3.3.2.3.8 Methanol......Page 778
44.3.2.3.5 Fuel Cell Core......Page 779
44.3.5 Energy Source System Management: Hybrid Systems......Page 780
44.4.2.1 Cartridges......Page 781
References......Page 782
45.1 Introduction......Page 784
45.2.1 Battery Energy Density as a Lagging Trend......Page 785
45.2.2 Trading Storage and Processing for Wireless Connectivity......Page 786
45.3.1 Catching the Ambience......Page 787
45.3.2 Get on the Beam......Page 788
45.4 Power from the People......Page 789
45.5 Hot Bodies: Power from Body Heat......Page 791
45.6 Heavy Breathing: Power From Respiration......Page 792
45.8 Shaking It Up: Power from Inertial Microsystems......Page 793
45.9 Power Typing......Page 795
45.10 Hand Waving: Power from Arm Motion......Page 797
45.12.1 Power from Walking......Page 799
45.12.2 Piezoelectric Materials......Page 800
45.12.3 Piezoelectric Shoe Inserts and Elastomer Heels......Page 802
45.12.4 Rotary Generator Conversion......Page 807
45.12.6 Getting Off Your Feet......Page 809
References......Page 810
46.1 Introduction and Technology Situation......Page 819
46.2 Sources of Chip Power Consumption and Effects of Heat Production......Page 821
46.3.3 Heat Spreaders......Page 822
46.3.9 Chip Cooling for Different Chip Categories......Page 823
46.5 Conclusions......Page 824
References......Page 825
Low-Power Electronics Design......Page 826
Computer Engineering Series......Page 827
Organization......Page 830
Acknowledgments......Page 831
Editor-in-Chief......Page 832
Contributors......Page 833
Contents......Page 838