Low-Power Design of Nanometer FPGAs: Architecture and EDA (Systems on Silicon)

Cover Page\r......Page 1
Copyright......Page 2
Dedication......Page 3
Author Bios\r......Page 4
1 FPGA Overview: Architecture and CAD......Page 6
Introduction......Page 7
FPGA Logic Resources Architecture......Page 10
Altera Stratix IV Logic Resources......Page 11
Xilinx Virtex-5 Logic Resources......Page 12
Actel ProASIC3/IGLOO Logic Resources......Page 13
Actel Axcelerator Logic Resources......Page 14
FPGA Routing Resources Architecture......Page 15
Logic Synthesis......Page 17
Packing......Page 18
Placement......Page 19
Routing......Page 21
VPR Architectural Assumptions......Page 22
Basic Logic Packing Algorithm: VPack......Page 27
Timing-Driven Logic Block Packing: T-VPack......Page 29
Placement: VPR......Page 31
Routing: VPR......Page 33
2 Power Dissipation in Modern FPGAs......Page 35
CMOS Technology Scaling Trends and Power Dissipation in VLSI Circuits......Page 36
CMOS Device Leakage Mechanisms......Page 39
Current Situation of Leakage Power in Nanometer FPGAs......Page 42
3 Power Estimation in FPGAs......Page 44
Introduction......Page 45
Simulation-Based Power Estimation Techniques......Page 47
Probabilistic-Based Power Estimation Techniques......Page 50
Spreadsheet Power Estimation Tools......Page 53
CAD Power Estimation Tools......Page 54
A Survey of FPGA Power Estimation Techniques......Page 56
Linear Regression-Based Power Modeling......Page 57
Look-up Table--Based FPGA Power Models......Page 59
Spatial Correlation and Signal Probability Calculations......Page 61
Exploration Phase: Locating Spatial Correlation......Page 63
Signal Probabilities Calculation Algorithm under Spatial Correlation......Page 64
Power Calculations Due to Glitches......Page 68
Signal Probabilities and Power Dissipation......Page 69
Results and Discussion......Page 74
4 Dynamic Power Reduction Techniques in FPGAs......Page 87
Multiple Supply Voltages......Page 88
Predefined Dual-VDD Dual-VTH FPGAs......Page 89
Programmable Dual-VDD......Page 94
Other Dual-VDD FPGA Techniques......Page 99
Glitch Power Reduction Using Delay Insertion......Page 101
Multiphase Flip-Flop Insertion for Glitch Power Reduction in FPGAs......Page 107
Negative Edge Flip-Flop Insertion for Glitch Power Reduction in FPGAs......Page 117
Behavioral Synthesis with Flip-Flop Insertion for Glitch Power Reduction in FPGAs......Page 119
Power Reduction Techniques during Technology Mapping......Page 124
Power Reduction Techniques during Clustering......Page 134
Power Reduction Techniques during Placement and Routing......Page 136
5 Leakage Power Reduction in FPGAs Using MTCMOS Techniques......Page 141
Introduction......Page 142
MTCMOS FPGA Architecture......Page 145
Sleep Transistor Sizing......Page 150
Mutually Exclusive Discharge Current Processing......Page 153
Logic-Based Discharge Current Processing......Page 155
Topological Sorting and Discharge Current Addition......Page 156
Activity Profile Generation......Page 160
Connection-Based Activity Profile GenerationAlgorithm (CAP)......Page 162
LAP Generation......Page 168
Activity Packing Algorithms......Page 176
AT-VPack......Page 177
Force-Based Activity T-VPack (FAT-VPack)......Page 179
Timing-Driven MTCMOS (T-MTCMOS) AT-VPack......Page 180
Power Estimation......Page 182
Results and Discussion......Page 183
Experimental Setup......Page 184
Algorithm Comparison......Page 185
Impact of Activity Packing on Performance......Page 188
Leakage Savings Breakdown......Page 191
Impact of Utilization and ON Time on Leakage Savings......Page 193
Impact of the Sleep Region Size......Page 195
Scalability of the Proposed Algorithms withTechnology Scaling......Page 196
6 Leakage Power Reduction in FPGAs Through Input Pin Reordering......Page 197
Subthreshold Leakage Current......Page 199
Gate Leakage......Page 202
Low-Leakage States in Pass-Transistor Multiplexers......Page 203
Leakage Power in Inverters/Buffers......Page 204
The Input Pin Reordering Algorithm......Page 206
LPR Algorithm......Page 207
Routing Switch Pin Reordering (RPR) Algorithm......Page 212
Experimental Results......Page 214
Pin Reordering and Performance......Page 217
Pin Reordering and Technology Scaling......Page 220
Conclusion......Page 221
References......Page 222
D......Page 237
L......Page 238
P......Page 239
T......Page 240
X......Page 241