Leakage in Nanometer CMOS Technologies

Contents......Page 6
Preface......Page 10
1.1 Introduction......Page 12
1.2 Sources......Page 14
1.3 Impact......Page 22
1.4 Solutions......Page 24
References......Page 29
2.1 Introduction......Page 31
2.2 Stack Effect......Page 33
2.3 Leakage Reduction using Natural Stacks......Page 40
2.4 Leakage Reduction using Forced Stacks......Page 45
2.5 Summary......Page 48
References......Page 49
3.2 Power Gating......Page 50
3.3 Dynamic Voltage Scaling......Page 73
References......Page 82
4.1 Introduction......Page 85
4.2 Power Gating Methodologies for Real Designs......Page 87
4.3 Future Directions of Power Gating......Page 98
4.4 Summary......Page 110
References......Page 111
5.1 Introduction......Page 113
5.2 Reverse Body Bias......Page 115
5.3 Forward Body Bias......Page 134
5.4 Future Directions......Page 145
References......Page 147
6.1 Introduction......Page 149
6.2 Bi-directional Adaptive Body Bias......Page 151
6.3 Body Bias Circuit Impedance......Page 158
6.4 Adaptive Supply Voltage and Adaptive Body Bias......Page 164
References......Page 170
7.1 Introduction......Page 171
7.2 Leakage in RAMs......Page 172
7.3 Leakage Sources and Reduction in RAMs......Page 176
7.4 Various Leakage Reduction Schemes......Page 179
7.5 Gate-Source Reverse Biasing Schemes......Page 183
7.6 Applications to RAM Cells......Page 188
7.7 Applications to Peripheral Circuits......Page 194
7.8 Future Prospects......Page 203
References......Page 204
8.1 Introduction......Page 208
8.2 Standby Techniques for Active Leakage Reduction......Page 209
8.3 Multi-performance Devices......Page 215
References......Page 216
9.1 Introduction......Page 217
9.2 Background......Page 218
9.3 Leakage vs. Frequency Characterization......Page 220
9.4 Multiple-Parameter Testing......Page 222
9.5 Sensitivity Gain with RBB and Temperature......Page 224
9.6 Leakage versus Temperature Two-Parameter Test Solution......Page 233
9.7 Discussions and Test Applications......Page 235
References......Page 238
10.1 Leakage Reduction Using Body Bias in a RISC Microprocessor......Page 240
10.2 Leakage Reduction in Application Processor in 3G Cellular Phone......Page 245
10.3 Leakage Reduction in SRAM module......Page 254
References......Page 260
11.1 Introduction......Page 261
11.2 Circuit Configuration and Operation......Page 265
11.3 Regulator Design......Page 271
11.4 Time-Division Multiplexed Operation......Page 277
11.5 SOC Design Issues and Future Trends......Page 280
11.6 Conclusion......Page 282
References......Page 283
12.1 Introduction......Page 285
12.2 Sub-threshold Leakage in Nanoscale Planar Si MOSFETs......Page 286
12.4 Offset Spacers to Reduce Edge Direct Tunneling Current......Page 290
12.5 Compensation Implants to Reduce Junction Leakage......Page 291
12.6 Source/Drain Extension Grading to Reduce Gate Induced Drain Leakage (GIDL)......Page 293
12.7 Future Solutions......Page 295
References......Page 302
C......Page 304
G......Page 305
L......Page 306
O......Page 307
R......Page 308
T......Page 309
Z......Page 310