Intel® Virtualization Technology for Directed I/O: Architecture Specification

1
2
3
Introduction
1.1
1.2
1.3
Overview
2.1
2.2
2.3
2.4
2.5
DMA3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Audience ........................................................................................................ 1-1
Glossary ........................................................................................................ 1-2
References ..................................................................................................... 1-3
Intel® Virtualization Technology Overview .......................................................... 2-1
VMM and Virtual Machines ................................................................................ 2-1
Hardware Support for Processor Virtualization ..................................................... 2-1
I/O Virtualization............................................................................................. 2-2
Intel® Virtualization Technology For Directed I/O Overview ................................... 2-2
2.5.1 Hardware Support for DMA Remapping..................................................... 2-3
2.5.1.1 OS Usages of DMA Remapping................................................... 2-3
2.5.1.2 VMM Usages of DMA Remapping ................................................ 2-4
2.5.1.3 DMA Remapping Usages by Guests............................................. 2-4
2.5.1.4 Interaction with Processor Virtualization...................................... 2-5
2.5.2 Hardware Support for Interrupt Remapping .............................................. 2-6
2.5.2.1 Interrupt Isolation.................................................................... 2-6
2.5.2.2 Interrupt Migration................................................................... 2-6
2.5.2.3 x2APIC Support ....................................................................... 2-6
2.5.3 Hardware Support for Interrupt Posting .................................................... 2-7
2.5.3.1 Interrupt Vector Scalability........................................................ 2-7
2.5.3.2 Interrupt Virtualization Efficiency ............................................... 2-7
2.5.3.3 Virtual Interrupt Migration......................................................... 2-7
Remapping
Types of DMA requests..................................................................................... 3-1
Domains and Address Translation ...................................................................... 3-1
Remapping Hardware - Software View................................................................ 3-2
Mapping Devices to Domains ............................................................................ 3-2
3.4.1 Source Identifier ................................................................................... 3-3
3.4.2 Root-Entry & Extended-Root-Entry .......................................................... 3-3
3.4.3 Context-Entry ....................................................................................... 3-4
3.4.4 Extended-Context-Entry ......................................................................... 3-5
Hierarchical Translation Structures..................................................................... 3-7
First-Level Translation...................................................................................... 3-9
3.6.1 Translation Faults ................................................................................ 3-11
3.6.2 Access Rights ..................................................................................... 3-11
3.6.3 Accessed, Extended Accessed, and Dirty Flags ........................................ 3-12
3.6.4 Snoop Behavior................................................................................... 3-13
3.6.5 Memory Typing ................................................................................... 3-13
3.6.5.1 Selecting Memory Type from Page Attribute Table ...................... 3-14
3.6.5.2 Selecting Memory Type from Memory Type Range Registers ........ 3-14
3.6.5.3 Selecting Effective Memory Type.............................................. 3-15
Second-Level Translation................................................................................ 3-16
3.7.1 Translation Faults ................................................................................ 3-19
3.7.2 Access Rights ..................................................................................... 3-19
3.7.3 Snoop Behavior................................................................................... 3-20
3.7.4 Memory Typing ................................................................................... 3-20
Nested Translation ........................................................................................ 3-21
3.8.1 Translation Faults ................................................................................ 3-22
3.8.2 Access Rights ..................................................................................... 3-22
3.8.3 Snoop Behavior................................................................................... 3-23
3.8.4 Memory Typing ................................................................................... 3-24
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Intel® Virtualization Technology for Directed I/O—Contents
3.9
4
3.10
3.11
3.12
3.13
3.14
3.15
Support4.1
4.2
5
4.3
Interrupt5.1
5.2
6
Caching6.1
6.2
Identifying Origination of DMA Requests ........................................................... 3-25
3.9.1 Devices Behind PCI-Express to PCI/PCI-X Bridges ....................................3-25
3.9.2 Devices Behind Conventional PCI Bridges ................................................3-25
3.9.3 Root-Complex Integrated Devices ..........................................................3-25
3.9.4 PCI-Express Devices Using Phantom Functions.........................................3-25
Handling Requests from Processor Graphics Device ............................................ 3-26
Handling Requests Crossing Page Boundaries .................................................... 3-26
Handling of Zero-Length Reads........................................................................ 3-26
Handling Requests to Interrupt Address Range .................................................. 3-27
Handling Requests to Reserved System Memory ................................................ 3-27
Root-Complex Peer to Peer Considerations ........................................................ 3-28
For Device-TLBs
Device-TLB Operation...................................................................................... 4-1
4.1.1 Translation Request .............................................................................. 4-2
4.1.2 Translation Completion .......................................................................... 4-2
4.1.3 Translated Request ............................................................................... 4-3
4.1.4 Invalidation Request & Completion .......................................................... 4-3
Remapping Hardware Handling of Device-TLBs ................................................... 4-4
4.2.1 Handling of ATS Protocol Errors .............................................................. 4-4
4.2.2 Root-Port Control of ATS Address Types................................................... 4-4
4.2.3 Handling of Translation Requests ............................................................ 4-4
4.2.3.1 Accessed, Extended Accessed, and Dirty Flags ............................ 4-8
4.2.3.2 Translation Requests for Multiple Translations ............................. 4-9
4.2.4 Handling of Translated Requests ............................................................. 4-9
Handling of Device-TLB Invalidations ................................................................ 4-10
Remapping and Interrupt Posting
Interrupt Remapping ....................................................................................... 5-1
5.1.1 Identifying Origination of Interrupt Requests ............................................ 5-1
5.1.2 Interrupt Request Formats On Intel® 64 Platforms ................................... 5-2
5.1.2.1 Interrupt Requests in Compatibility Format ................................. 5-2
5.1.2.2 Interrupt Requests in Remappable Format .................................. 5-3
5.1.3 Interrupt Remapping Table .................................................................... 5-4
5.1.4 Interrupt-Remapping Hardware Operation................................................ 5-4
5.1.4.1 Interrupt Remapping Fault Conditions ........................................ 5-6
5.1.5 Programming Interrupt Sources To Generate Remappable Interrupts ........... 5-6
5.1.5.1 I/OxAPIC Programming ............................................................ 5-7
5.1.5.2 MSI and MSI-X Register Programming........................................ 5-8
5.1.6 Remapping Hardware - Interrupt Programming......................................... 5-9
5.1.7 Programming in Intel® 64 xAPIC Mode .................................................... 5-9
5.1.8 Programming in Intel® 64 x2APIC Mode..................................................5-10
5.1.9 Handling of Platform Events ..................................................................5-10
Interrupt Posting ........................................................................................... 5-11
5.2.1 Interrupt Remapping Table Support for Interrupt Posting ..........................5-11
5.2.2 Posted Interrupt Descriptor ...................................................................5-12
5.2.3 Interrupt-Posting Hardware Operation ....................................................5-12
5.2.4 Ordering Requirements for Interrupt Posting ...........................................5-13
5.2.5 Using Interrupt Posting for Virtual Interrupt Delivery ................................5-13
5.2.6 Interrupt Posting for Level Triggered Interrupts .......................................5-15
Translation Information
Caching Mode.................................................................................................
 6-1
Address Translation Caches..............................................................................
 6-1
6.2.1 Tagging of Cached Translations ..............................................................
 6-2
6.2.2 Context-cache ......................................................................................
 6-2
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Contents—Intel® Virtualization Technology for Directed I/O
6.3
6.4
6.5
7
6.6
6.7
6.8
6.9
6.10
Translation7.1
7.2
6.2.2.1 Context-Entry Programming Considerations................................. 6-4
6.2.3
 PASID-cache ........................................................................................ 6-4
6.2.4
 IOTLB .................................................................................................. 6-5
6.2.4.1 Details of IOTLB Use ................................................................ 6-6
6.2.4.2 Global Pages ........................................................................... 6-7
6.2.5 Caches for Paging Structures .................................................................. 6-7
6.2.5.1 PML4-cache ............................................................................ 6-8
6.2.5.2 PDPE-cache............................................................................. 6-9
6.2.5.3 PDE-cache ............................................................................ 6-11
6.2.5.4 Details of Paging-Structure Cache Use ...................................... 6-12
6.2.6 Using the Paging-Structure Caches to Translate Requests ......................... 6-13
6.2.7 Multiple Cached Entries for a Single Paging-Structure Entry....................... 6-14
Translation Caching at Endpoint Device ............................................................ 6-15
Interrupt Entry Cache .................................................................................... 6-15
Invalidation of Translation Caches ................................................................... 6-15
6.5.1 Register-based Invalidation Interface ..................................................... 6-16
6.5.1.1 Context Command Register ..................................................... 6-16
6.5.1.2 IOTLB Registers..................................................................... 6-16
6.5.2 Queued Invalidation Interface ............................................................... 6-17
6.5.2.1 Context-cache Invalidate Descriptor ......................................... 6-19
6.5.2.2 PASID-cache Invalidate Descriptor ........................................... 6-20
6.5.2.3 IOTLB Invalidate Descriptor..................................................... 6-21
6.5.2.4 Extended IOTLB Invalidate Descriptor....................................... 6-22
6.5.2.5 Device-TLB Invalidate Descriptor ............................................. 6-24
6.5.2.6 Extended Device-TLB Invalidate Descriptor................................ 6-25
6.5.2.7 Interrupt Entry Cache Invalidate Descriptor ............................... 6-26
6.5.2.8 Invalidation Wait Descriptor .................................................... 6-27
6.5.2.9 Hardware Generation of Invalidation Completion Events.............. 6-27
6.5.2.10 Hardware Handling of Queued Invalidation Interface Errors ......... 6-28
6.5.2.11 Queued Invalidation Ordering Considerations............................. 6-29
6.5.3 IOTLB Invalidation Considerations ......................................................... 6-29
6.5.3.1 Implicit Invalidation on Page Requests ...................................... 6-29
6.5.3.2 Caching Fractured Translations ................................................ 6-30
6.5.3.3 Recommended Invalidation ..................................................... 6-30
6.5.3.4 Optional Invalidation .............................................................. 6-31
6.5.3.5 Delayed Invalidation .............................................................. 6-32
6.5.4 TLB Shootdown Optimization for Root-Complex Integrated Devices ............ 6-32
6.5.4.1 Deferred Invalidation.............................................................. 6-33
6.5.4.2 PASID-State Table ................................................................. 6-34
6.5.4.3 Remapping Hardware Handling of PASID State-Update Requests .. 6-35
6.5.4.4 Root-Complex Integrated Device Handling of PASID State-Update
Responses ............................................................................ 6-35
6.5.4.5 Ordering of PASID State-Update Requests and Responses ........... 6-36
6.5.4.6 Example TLB Shootdown using Deferred Invalidations................. 6-36
6.5.5 Draining of Requests to Memory............................................................ 6-36
6.5.6 Interrupt Draining ............................................................................... 6-37
Set Root Table Pointer Operation ..................................................................... 6-38
Set Interrupt Remapping Table Pointer Operation .............................................. 6-38
Write Buffer Flushing ..................................................................................... 6-39
Hardware Register Programming Considerations ................................................ 6-39
Sharing Remapping Structures Across Hardware Units........................................ 6-39
Faults
Interrupt Translation Faults .............................................................................. 7-1
Address Translation Faults ................................................................................ 7-1
7.2.1 Non-Recoverable Address Translation Faults ............................................. 7-2
7.2.1.1 Non-Recoverable Faults for Untranslated Requests Without PASID .. 7-2
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Intel® Virtualization Technology for Directed I/O—Contents
7.3
7.4
7.5
7.6
7.7
8
7.8
7.9
7.10
7.11
7.12
BIOS
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9
Translation9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.107.2.1.2 Non-Recoverable Faults for Untranslated Requests With PASID...... 7-3
7.2.1.3 Non-Recoverable Faults for Translation Requests Without PASID.... 7-6
7.2.1.4 Non-Recoverable Faults for Translation Requests With PASID ........ 7-6
7.2.1.5 Non-Recoverable Faults for Translated Requests.......................... 7-8
7.2.2 Recoverable Address Translation Faults ................................................... 7-9
Non-Recoverable Fault Reporting ..................................................................... 7-10
7.3.1 Primary Fault Logging...........................................................................7-11
7.3.2 Advanced Fault Logging ........................................................................7-11
Non-Recoverable Fault Event........................................................................... 7-12
Recoverable Fault Reporting ............................................................................ 7-13
7.5.1 Handling of Page Requests ....................................................................7-13
7.5.1.1 Page Request Descriptor .........................................................7-15
Recoverable Fault Event ................................................................................. 7-17
Servicing Recoverable Faults ........................................................................... 7-18
7.7.1 Page Group Response Descriptor ...........................................................7-19
7.7.2 Page Stream Response Descriptor..........................................................7-20
Page Request Ordering and Draining ................................................................ 7-21
Page Response Ordering and Draining .............................................................. 7-21
Pending Page Request Handling on Terminal Conditions ...................................... 7-22
Software Steps to Drain Page Requests & Responses .......................................... 7-22
Revoking PASIDs with Pending Page Faults ....................................................... 7-23
Considerations
DMA Remapping Reporting Structure................................................................. 8-1
Remapping Structure Types ............................................................................. 8-2
DMA Remapping Hardware Unit Definition Structure ............................................ 8-3
8.3.1 Device Scope Structure ......................................................................... 8-4
8.3.1.1 Reporting Scope for I/OxAPICs.................................................. 8-6
8.3.1.2 Reporting Scope for MSI Capable HPET Timer Block ..................... 8-6
8.3.1.3 Reporting Scope for ACPI Name-space Devices............................ 8-6
8.3.1.4 Device Scope Example ............................................................. 8-6
8.3.2 Implications for ARI .............................................................................. 8-8
8.3.3 Implications for SR-IOV ......................................................................... 8-8
8.3.4 Implications for PCI/PCI-Express Hot Plug ................................................ 8-8
8.3.5 Implications with PCI Resource Rebalancing ............................................. 8-8
8.3.6 Implications with Provisioning PCI BAR Resources ..................................... 8-8
Reserved Memory Region Reporting Structure .................................................... 8-9
Root Port ATS Capability Reporting Structure..................................................... 8-10
Remapping Hardware Static Affinity Structure.................................................... 8-11
ACPI Name-space Device Declaration Structure ................................................. 8-12
Remapping Hardware Unit Hot Plug .................................................................. 8-12
8.8.1 ACPI Name Space Mapping ...................................................................8-12
8.8.2 ACPI Sample Code ...............................................................................8-13
8.8.3 Example Remapping Hardware Reporting Sequence..................................8-14
Structure Formats
Root Entry ..................................................................................................... 9-1
Extended Root Entry ....................................................................................... 9-3
Context Entry................................................................................................. 9-5
Extended-Context-Entry .................................................................................. 9-8
PASID Entry.................................................................................................. 9-15
PASID-State Entry ......................................................................................... 9-17
First-Level Paging Entries................................................................................ 9-18
Second-Level Paging Entries............................................................................ 9-25
Fault Record ................................................................................................. 9-32
Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts ........................ 9-34
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Contents—Intel® Virtualization Technology for Directed I/O
10
9.11
9.12
Register10.110.210.310.4A
 Non-RecoverableInterrupt Remapping Table Entry (IRTE) for Posted Interrupts ............................. 9-39
Posted Interrupt Descriptor (PID) .................................................................... 9-42
Descriptions
Register Location........................................................................................... 10-1
Software Access to Registers .......................................................................... 10-1
Register Attributes ........................................................................................ 10-2
Register Descriptions ..................................................................................... 10-3
10.4.1 Version Register.................................................................................. 10-7
10.4.2 Capability Register .............................................................................. 10-8
10.4.3 Extended Capability Register............................................................... 10-13
10.4.4 Global Command Register .................................................................. 10-17
10.4.5 Global Status Register........................................................................ 10-22
10.4.6 Root Table Address Register ............................................................... 10-24
10.4.7 Context Command Register ................................................................ 10-25
10.4.8 IOTLB Registers ................................................................................ 10-28
10.4.8.1 IOTLB Invalidate Register ..................................................... 10-29
10.4.8.2 Invalidate Address Register ................................................... 10-32
10.4.9 Fault Status Register ......................................................................... 10-34
10.4.10Fault Event Control Register ............................................................... 10-36
10.4.11Fault Event Data Register ................................................................... 10-38
10.4.12Fault Event Address Register .............................................................. 10-39
10.4.13Fault Event Upper Address Register ..................................................... 10-40
10.4.14Fault Recording Registers [n] .............................................................. 10-41
10.4.15Advanced Fault Log Register ............................................................... 10-44
10.4.16Protected Memory Enable Register....................................................... 10-45
10.4.17Protected Low-Memory Base Register................................................... 10-47
10.4.18Protected Low-Memory Limit Register .................................................. 10-48
10.4.19Protected High-Memory Base Register .................................................. 10-49
10.4.20Protected High-Memory Limit Register.................................................. 10-50
10.4.21Invalidation Queue Head Register ........................................................ 10-51
10.4.22Invalidation Queue Tail Register .......................................................... 10-52
10.4.23Invalidation Queue Address Register .................................................... 10-53
10.4.24Invalidation Completion Status Register ............................................... 10-54
10.4.25Invalidation Event Control Register ...................................................... 10-55
10.4.26Invalidation Event Data Register ......................................................... 10-56
10.4.27Invalidation Event Address Register ..................................................... 10-57
10.4.28Invalidation Event Upper Address Register ............................................ 10-58
10.4.29Interrupt Remapping Table Address Register......................................... 10-59
10.4.30Page Request Queue Head Register ..................................................... 10-60
10.4.31Page Request Queue Tail Register........................................................ 10-61
10.4.32Page Request Queue Address Register ................................................. 10-62
10.4.33Page Request Status Register ............................................................. 10-63
10.4.34Page Request Event Control Register ................................................... 10-64
10.4.35Page Request Event Data Register ....................................................... 10-65
10.4.36Page Request Event Address Register................................................... 10-66
10.4.37Page Request Event Upper Address Register ......................................... 10-67
10.4.38MTRR Capability Register.................................................................... 10-68
10.4.39MTRR Default Type Register................................................................ 10-69
10.4.40Fixed-Range MTRRs ........................................................................... 10-70
10.4.41Variable-Range MTRRs ....................................................................... 10-72
Fault Reason Encodings ................................................................. 1
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Intel® Virtualization Technology for Directed I/O—Contents
Figures
Figure
 1-1.
 General Platform Topology ......................................................................... 1-1
Figure
 2-2.
 Example OS Usage of DMA Remapping ........................................................ 2-3
Figure
 2-3.
 Example Virtualization Usage of DMA Remapping .......................................... 2-4
Figure
 2-4.
 Interaction Between I/O and Processor Virtualization ..................................... 2-5
Figure
 3-5.
 DMA Address Translation ........................................................................... 3-2
Figure
 3-6.
 Requester Identifier Format........................................................................ 3-3
Figure
 3-7.
 Device to Domain Mapping Structures using Root-Table ................................. 3-4
Figure
 3-8.
 Device to Domain Mapping Structures using Extended-Root-Table ................... 3-6
Figure
 3-9.
 Address Translation to a 4-KByte Page......................................................... 3-7
Figure
 3-10.
 Address Translation to a 2-MByte Large Page................................................ 3-8
Figure
 3-11.
 Address Translation to a 1-GByte Large Page ................................................ 3-8
Figure
 3-12.
 Nested Translation with 4-KByte pages .......................................................3-21
Figure
 4-13.
 Device-TLB Operation ................................................................................ 4-1
Figure
 5-14.
 Compatibility Format Interrupt Request........................................................ 5-2
Figure
 5-15.
 Remappable Format Interrupt Request......................................................... 5-3
Figure
 5-16.
 I/OxAPIC RTE Programming ....................................................................... 5-7
Figure
 5-17.
 MSI-X Programming .................................................................................. 5-8
Figure
 5-18.
 Remapping Hardware Interrupt Programming in Intel® 64 xAPIC Mode............ 5-9
Figure
 5-19.
 Remapping Hardware Interrupt Programming in Intel® 64 x2APIC Mode .........5-10
Figure
 6-20.
 Context-cache Invalidate Descriptor ...........................................................6-19
Figure
 6-21.
 PASID-cache Invalidate Descriptor .............................................................6-20
Figure
 6-22.
 IOTLB Invalidate Descriptor.......................................................................6-21
Figure
 6-23.
 Extended IOTLB Invalidate Descriptor .........................................................6-22
Figure
 6-24.
 Device-TLB Invalidate Descriptor................................................................6-24
Figure
 6-25.
 Extended Device-TLB Invalidate Descriptor ..................................................6-25
Figure
 6-26.
 Interrupt Entry Cache Invalidate Descriptor .................................................6-26
Figure
 6-27.
 Invalidation Wait Descriptor ......................................................................6-27
Figure
 7-28.
 Page Request Descriptor ...........................................................................7-15
Figure
 7-29.
 Page Group Response Descriptor................................................................7-19
Figure
 7-30.
 Page Stream Response Descriptor ..............................................................7-20
Figure
 8-31.
 Hypothetical Platform Configuration............................................................. 8-7
Figure
 9-32.
 Root-Entry Format .................................................................................... 9-1
Figure
 9-33.
 Extended-Root-Entry Format ...................................................................... 9-3
Figure
 9-34.
 Context-Entry Format ................................................................................ 9-5
Figure
 9-35.
 Extended-Context-Entry Format.................................................................. 9-8
Figure
 9-36.
 PASID Entry Format .................................................................................9-15
Figure
 9-37.
 PASID-State Entry Format.........................................................................9-17
Figure
 9-38.
 Format for First-Level Paging Entries ..........................................................9-18
Figure
 9-39.
 Format for Second-Level Paging Entries ......................................................9-25
Figure
 9-40.
 Fault-Record Format.................................................................................9-32
Figure
 9-41.
 Interrupt Remap Table Entry Format for Remapped Interrupts .......................9-34
Figure
 9-42.
 Interrupt Remap Table Entry Format for Posted Interrupts.............................9-39
Figure
 9-43.
 Posted Interrupt Descriptor Format ............................................................9-42
Figure
 10-44.
 Version Register ......................................................................................10-7
Figure
 10-45.
 Capability Register ...................................................................................10-8
Figure
 10-46.
 Extended Capability Register ................................................................... 10-13
Figure
 10-47.
 Global Command Register ....................................................................... 10-17
Figure
 10-48.
 Global Status Register ............................................................................ 10-22
Figure
 10-49.
 Root Table Address Register .................................................................... 10-24
Figure
 10-50.
 Context Command Register ..................................................................... 10-25
Figure
 10-51.
 IOTLB Invalidate Register........................................................................ 10-29
Figure
 10-52.
 Invalidate Address Register ..................................................................... 10-32
Figure
 10-53.
 Fault Status Register .............................................................................. 10-34
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Figure
 10-54.
 Fault Event Control Register.................................................................... 10-36
Figure
 10-55.
 Fault Event Data Register ....................................................................... 10-38
Figure
 10-56.
 Fault Event Address Register................................................................... 10-39
Figure
 10-57.
 Fault Event Upper Address Register.......................................................... 10-40
Figure
 10-58.
 Fault Recording Register ......................................................................... 10-41
Figure
 10-59.
 Advanced Fault Log Register ................................................................... 10-44
Figure
 10-60.
 Protected Memory Enable Register ........................................................... 10-45
Figure
 10-61.
 Protected Low-Memory Base Register ....................................................... 10-47
Figure
 10-62.
 Protected Low-Memory Limit Register....................................................... 10-48
Figure
 10-63.
 Protected High-Memory Base Register ...................................................... 10-49
Figure
 10-64.
 Protected High-Memory Limit Register ...................................................... 10-50
Figure
 10-65.
 Invalidation Queue Head Register ............................................................ 10-51
Figure
 10-66.
 Invalidation Queue Tail Register .............................................................. 10-52
Figure
 10-67.
 Invalidation Queue Address Register ........................................................ 10-53
Figure
 10-68.
 Invalidation Completion Status Register.................................................... 10-54
Figure
 10-69.
 Invalidation Event Control Register .......................................................... 10-55
Figure
 10-70.
 Invalidation Event Data Register.............................................................. 10-56
Figure
 10-71.
 Invalidation Event Address Register ......................................................... 10-57
Figure
 10-72.
 Invalidation Event Upper Address Register ................................................ 10-58
Figure
 10-73.
 Interrupt Remapping Table Address Register ............................................. 10-59
Figure
 10-74.
 Page Request Queue Head Register.......................................................... 10-60
Figure
 10-75.
 Page Request Queue Tail Register ............................................................ 10-61
Figure
 10-76.
 Page Request Queue Address Register...................................................... 10-62
Figure
 10-77.
 Page Request Status Register.................................................................. 10-63
Figure
 10-78.
 Page Request Event Control Register........................................................ 10-64
Figure
 10-79.
 Page Request Event Data Register ........................................................... 10-65
Figure
 10-80.
 Page Request Event Address Register ....................................................... 10-66
Figure
 10-81.
 Page Request Event Upper Address Register.............................................. 10-67
Figure
 10-82.
 MTRR Capability Register ........................................................................ 10-68
Figure
 10-83.
 MTRR Default Type Register .................................................................... 10-69
Figure
 10-84.
 Fixed-Range MTRR Format ...................................................................... 10-70
Figure
 10-85.
 Variable-Range MTRR Format .................................................................. 10-72
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Intel® Virtualization Technology for Directed I/O—Contents
Tables
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
Glossary .................................................................................................. 1-2
References ............................................................................................... 1-3
First-level Paging Structures ....................................................................... 3-9
Effective Memory Types ............................................................................3-15
Second-level Paging Structures ..................................................................3-17
Address Fields in Remappable Interrupt Request Format ................................ 5-3
Data Fields in Remappable Interrupt Request Format ..................................... 5-4
Interrupt Remapping Fault Conditions .......................................................... 5-6
Index Mask Programming..........................................................................6-26
Interrupt Remapping Fault Conditions .......................................................... 7-1
Non-Recoverable Faults for Untranslated Requests Without PASID ................... 7-2
Non-Recoverable Faults for Untranslated Requests With PASID ....................... 7-3
Non-Recoverable Faults For Translation Requests Without PASID..................... 7-6
Non-Recoverable Faults For Translation Requests With PASID ......................... 7-7
Non-Recoverable Faults For Translated Requests ........................................... 7-9
Recoverable Fault Conditions For Translation Requests ..................................7-10
Response Codes.......................................................................................7-20
Format of PML4E that references a Page-Directory-Pointer Table ....................9-19
Format of PDPE that maps a 1-GByte Page .................................................9-20
Format of PDPE that references a Page-Directory Table .................................9-21
Format of PDE that maps a 2-MByte Page ..................................................9-22
Format of PDE that references a Page Table.................................................9-23
Format of PTE that maps a 4-KByte Page ...................................................9-24
Format of SL-PML4E referencing a Second-Level-Page-Directory-Pointer Table .9-26
Format of SL-PDPE that maps a 1-GByte Page .............................................9-27
Format of SL-PDPE that references a Second-Level-Page-Directory .................9-28
Format of SL-PDE that maps to a 2-MByte Page ...........................................9-29
Format of SL-PDE that references a Second-Level-Page Table ........................9-30
Format of SL-PTE that maps 4-KByte Page ..................................................9-31
Address Mapping for Fixed-Range MTRRs .................................................. 10-71