Intel Pentium IV

1.1. IA-32 Processors Covered in this Manual......Page 20
1.3. Overview of the IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic ARchit.........Page 21
1.4. Overview of the IA-32 Intel Architecture Software Developer’s Manual, Volume 3: SYSTEM PROGR.........Page 23
1.5.1. Bit and Byte Order......Page 25
1.5.2. Reserved Bits and Software Compatibility......Page 26
1.5.5. Segmented Addressing......Page 27
1.5.6. Exceptions......Page 28
1.6. Related Literature......Page 29
2.2. Instruction Prefixes......Page 32
2.4. ModR/M and SIB Bytes......Page 34
2.6. Addressing-Mode Encoding of ModR/M and SIB Bytes......Page 35
3.1.1.1. Opcode Column......Page 42
3.1.1.2. Instruction Column......Page 43
3.1.2. Operation......Page 46
3.1.3. Intel C/C++ Compiler Intrinsics Equivalents......Page 49
3.1.3.3. SSE and SSE2 Intrinsics......Page 50
3.1.6. Protected Mode Exceptions......Page 52
3.1.7. Real-Address Mode Exceptions......Page 53
3.1.10. SIMD Floating-Point Exceptions......Page 54
3.2. Instruction reference......Page 55
AAA—ASCII Adjust After Addition......Page 56
AAD—ASCII Adjust AX Before Division......Page 57
AAM—ASCII Adjust AX After Multiply......Page 58
AAS—ASCII Adjust AL After Subtraction......Page 59
ADC—Add with Carry......Page 60
ADD—Add......Page 62
ADDPD—Add Packed Double-Precision Floating-Point Values......Page 64
ADDPS—Add Packed Single-Precision Floating-Point Values......Page 66
ADDSD—Add Scalar Double-Precision Floating-Point Values......Page 68
ADDSS—Add Scalar Single-Precision Floating-Point Values......Page 70
AND—Logical AND......Page 72
ANDPD—Bitwise Logical AND of Packed Double-Precision Floating-Point Values......Page 74
ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point Values......Page 76
ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values......Page 78
ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values......Page 80
ARPL—Adjust RPL Field of Segment Selector......Page 82
BOUND—Check Array Index Against Bounds......Page 84
BSF—Bit Scan Forward......Page 86
BSR—Bit Scan Reverse......Page 88
BSWAP—Byte Swap......Page 90
BT—Bit Test......Page 91
BTC—Bit Test and Complement......Page 93
BTR—Bit Test and Reset......Page 95
BTS—Bit Test and Set......Page 97
CALL—Call Procedure......Page 99
CBW/CWDE—Convert Byte to Word/Convert Word to Doubleword......Page 110
CDQ—Convert Double to Quad......Page 111
CLC—Clear Carry Flag......Page 112
CLD—Clear Direction Flag......Page 113
CLFLUSH—Flush Cache Line......Page 114
CLI—Clear Interrupt Flag......Page 116
CLTS—Clear Task-Switched Flag in CR0......Page 118
CMC—Complement Carry Flag......Page 119
CMOVcc—Conditional Move......Page 120
CMP—Compare Two Operands......Page 123
CMPPD—Compare Packed Double-Precision Floating-Point Values......Page 125
CMPPS—Compare Packed Single-Precision Floating-Point Values......Page 129
CMPS/CMPSB/CMPSW/CMPSD—Compare String Operands......Page 133
CMPSD—Compare Scalar Double-Precision Floating-Point Values......Page 136
CMPSS—Compare Scalar Single-Precision Floating-Point Values......Page 140
CMPXCHG—Compare and Exchange......Page 144
CMPXCHG8B—Compare and Exchange 8 Bytes......Page 146
COMISD—Compare Scalar Ordered Double-Precision Floating- Point Values and Set EFLAGS......Page 148
COMISS—Compare Scalar Ordered Single-Precision Floating- Point Values and Set EFLAGS......Page 151
CPUID—CPU Identification......Page 154
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values......Page 168
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values......Page 170
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers......Page 172
CVTPD2PI—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers......Page 174
CVTPD2PS—Covert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating.........Page 176
CVTPI2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values......Page 178
CVTPI2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values......Page 180
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers......Page 182
CVTPS2PD—Covert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating.........Page 184
CVTPS2PI—Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers......Page 186
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer......Page 188
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating.........Page 190
CVTSI2SD—Convert Doubleword Integer to Scalar Double- Precision Floating-Point Value......Page 192
CVTSI2SS—Convert Doubleword Integer to Scalar Single- Precision Floating-Point Value......Page 194
CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating.........Page 196
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer......Page 198
CVTTPD2PI—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doublew.........Page 200
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doublew.........Page 202
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doublew.........Page 204
CVTTPS2PI—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doublew.........Page 206
CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Doublewo.........Page 208
CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer......Page 210
CWD/CDQ—Convert Word to Doubleword/Convert Doubleword to Quadword......Page 212
CWDE—Convert Word to Doubleword......Page 213
DAA—Decimal Adjust AL after Addition......Page 214
DAS—Decimal Adjust AL after Subtraction......Page 216
DEC—Decrement by 1......Page 217
DIV—Unsigned Divide......Page 219
DIVPD—Divide Packed Double-Precision Floating-Point Values......Page 222
DIVPS—Divide Packed Single-Precision Floating-Point Values......Page 224
DIVSD—Divide Scalar Double-Precision Floating-Point Values......Page 226
DIVSS—Divide Scalar Single-Precision Floating-Point Values......Page 228
EMMS—Empty MMX State......Page 230
ENTER—Make Stack Frame for Procedure Parameters......Page 231
F2XM1—Compute 2x–1......Page 234
FABS—Absolute Value......Page 236
FADD/FADDP/FIADD—Add......Page 238
FBLD—Load Binary Coded Decimal......Page 241
FBSTP—Store BCD Integer and Pop......Page 243
FCHS—Change Sign......Page 246
FCLEX/FNCLEX—Clear Exceptions......Page 248
FCMOVcc—Floating-Point Conditional Move......Page 250
FCOM/FCOMP/FCOMPP—Compare Floating Point Values......Page 252
FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS......Page 255
FCOS—Cosine......Page 258
FDECSTP—Decrement Stack-Top Pointer......Page 260
FDIV/FDIVP/FIDIV—Divide......Page 261
FDIVR/FDIVRP/FIDIVR—Reverse Divide......Page 265
FFREE—Free Floating-Point Register......Page 269
FICOM/FICOMP—Compare Integer......Page 270
FILD—Load Integer......Page 272
FINCSTP—Increment Stack-Top Pointer......Page 274
FINIT/FNINIT—Initialize Floating-Point Unit......Page 275
FIST/FISTP—Store Integer......Page 277
FLD—Load Floating Point Value......Page 280
FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant......Page 282
FLDCW—Load x87 FPU Control Word......Page 284
FLDENV—Load x87 FPU Environment......Page 286
FMUL/FMULP/FIMUL—Multiply......Page 288
FNOP—No Operation......Page 291
FPATAN—Partial Arctangent......Page 292
FPREM—Partial Remainder......Page 294
FPREM1—Partial Remainder......Page 297
FPTAN—Partial Tangent......Page 300
FRNDINT—Round to Integer......Page 302
FRSTOR—Restore x87 FPU State......Page 303
FSAVE/FNSAVE—Store x87 FPU State......Page 305
FSCALE—Scale......Page 308
FSIN—Sine......Page 310
FSINCOS—Sine and Cosine......Page 312
FSQRT—Square Root......Page 314
FST/FSTP—Store Floating Point Value......Page 316
FSTCW/FNSTCW—Store x87 FPU Control Word......Page 319
FSTENV/FNSTENV—Store x87 FPU Environment......Page 321
FSTSW/FNSTSW—Store x87 FPU Status Word......Page 324
FSUB/FSUBP/FISUB—Subtract......Page 327
FSUBR/FSUBRP/FISUBR—Reverse Subtract......Page 330
FTST—TEST......Page 333
FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values......Page 335
FWAIT—Wait......Page 338
FXAM—Examine......Page 339
FXCH—Exchange Register Contents......Page 341
FXRSTOR—Restore x87 FPU, MMX, SSE, and SSE2 State......Page 343
FXSAVE—Save x87 FPU, MMX, SSE, and SSE2 State......Page 345
FXTRACT—Extract Exponent and Significand......Page 351
FYL2X—Compute y * log2x......Page 353
FYL2XP1—Compute y * log2(x +1)......Page 355
HLT—Halt......Page 357
IDIV—Signed Divide......Page 358
IMUL—Signed Multiply......Page 361
IN—Input from Port......Page 364
INC—Increment by 1......Page 366
INS/INSB/INSW/INSD—Input from Port to String......Page 368
INT n/INTO/INT 3—Call to Interrupt Procedure......Page 371
INVD—Invalidate Internal Caches......Page 383
INVLPG—Invalidate TLB Entry......Page 385
IRET/IRETD—Interrupt Return......Page 386
Jcc—Jump if Condition Is Met......Page 394
JMP—Jump......Page 398
LAHF—Load Status Flags into AH Register......Page 405
LAR—Load Access Rights Byte......Page 406
LDMXCSR—Load MXCSR Register......Page 409
LDS/LES/LFS/LGS/LSS—Load Far Pointer......Page 411
LEA—Load Effective Address......Page 414
LEAVE—High Level Procedure Exit......Page 416
LES—Load Full Pointer......Page 418
LFENCE—Load Fence......Page 419
LFS—Load Full Pointer......Page 420
LGDT/LIDT—Load Global/Interrupt Descriptor Table Register......Page 421
LGS—Load Full Pointer......Page 423
LLDT—Load Local Descriptor Table Register......Page 424
LIDT—Load Interrupt Descriptor Table Register......Page 426
LMSW—Load Machine Status Word......Page 427
LOCK—Assert LOCK# Signal Prefix......Page 429
LODS/LODSB/LODSW/LODSD—Load String......Page 431
LOOP/LOOPcc—Loop According to ECX Counter......Page 434
LSL—Load Segment Limit......Page 436
LSS—Load Full Pointer......Page 439
LTR—Load Task Register......Page 440
MASKMOVDQU—Store Selected Bytes of Double Quadword......Page 442
MASKMOVQ—Store Selected Bytes of Quadword......Page 444
MAXPD—Return Maximum Packed Double-Precision Floating- Point Values......Page 447
MAXPS—Return Maximum Packed Single-Precision Floating-Point Values......Page 450
MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value......Page 453
MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value......Page 456
MFENCE—Memory Fence......Page 459
MINPD—Return Minimum Packed Double-Precision Floating-Point Values......Page 460
MINPS—Return Minimum Packed Single-Precision Floating-Point Values......Page 463
MINSD—Return Minimum Scalar Double-Precision Floating-Point Value......Page 466
MINSS—Return Minimum Scalar Single-Precision Floating-Point Value......Page 469
MOV—Move......Page 472
MOV—Move to/from Control Registers......Page 477
MOV—Move to/from Debug Registers......Page 479
MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values......Page 481
MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values......Page 483
MOVD—Move Doubleword......Page 485
MOVDQA—Move Aligned Double Quadword......Page 487
MOVDQU—Move Unaligned Double Quadword......Page 489
MOVDQ2Q—Move Quadword from XMM to MMX Register......Page 491
MOVHLPS— Move Packed Single-Precision Floating-Point Values High to Low......Page 492
MOVHPD—Move High Packed Double-Precision Floating-Point Value......Page 493
MOVHPS—Move High Packed Single-Precision Floating-Point Values......Page 495
MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High......Page 497
MOVLPD—Move Low Packed Double-Precision Floating-Point Value......Page 498
MOVLPS—Move Low Packed Single-Precision Floating-Point Values......Page 500
MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask......Page 502
MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask......Page 504
MOVNTDQ—Store Double Quadword Using Non-Temporal Hint......Page 506
MOVNTI—Store Doubleword Using Non-Temporal Hint......Page 508
MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint......Page 510
MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint......Page 512
MOVNTQ—Store of Quadword Using Non-Temporal Hint......Page 514
MOVQ—Move Quadword......Page 516
MOVQ2DQ—Move Quadword from MMX to XMM Register......Page 518
MOVS/MOVSB/MOVSW/MOVSD—Move Data from StringtoString......Page 519
MOVSD—Move Scalar Double-Precision Floating-Point Value......Page 522
MOVSS—Move Scalar Single--Precision Floating-Point Values......Page 525
MOVSX—Move with Sign-Extension......Page 528
MOVUPD—Move Unaligned Packed Double-Precision Floating- Point Values......Page 530
MOVUPS—Move Unaligned Packed Single-Precision Floating- Point Values......Page 532
MOVZX—Move with Zero-Extend......Page 534
MUL—Unsigned Multiply......Page 536
MULPD—Multiply Packed Double-Precision Floating-Point Values......Page 538
MULPS—Multiply Packed Single-Precision Floating-Point Values......Page 540
MULSD—Multiply Scalar Double-Precision Floating-Point Values......Page 542
MULSS—Multiply Scalar Single-Precision Floating-Point Values......Page 544
NEG—Two's Complement Negation......Page 546
NOP—No Operation......Page 548
NOT—One's Complement Negation......Page 549
OR—Logical Inclusive OR......Page 551
ORPD—Bitwise Logical OR of Double-Precision Floating-Point Values......Page 553
ORPS—Bitwise Logical OR of Single-Precision Floating-Point Values......Page 555
OUT—Output to Port......Page 557
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port......Page 559
PACKSSWB/PACKSSDW—Pack with Signed Saturation......Page 562
PACKUSWB—Pack with Unsigned Saturation......Page 566
PADDB/PADDW/PADDD—Add Packed Integers......Page 569
PADDQ—Add Packed Quadword Integers......Page 572
PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation......Page 574
PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation......Page 577
PAND—Logical AND......Page 580
PANDN—Logical AND NOT......Page 582
PAUSE—Spin Loop Hint......Page 584
PAVGB/PAVGW—Average Packed Integers......Page 585
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal......Page 588
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than......Page 592
PEXTRW—Extract Word......Page 596
PINSRW—Insert Word......Page 598
PMADDWD—Multiply and Add Packed Integers......Page 601
PMAXSW—Maximum of Packed Signed Word Integers......Page 604
PMAXUB—Maximum of Packed Unsigned Byte Integers......Page 607
PMINSW—Minimum of Packed Signed Word Integers......Page 610
PMINUB—Minimum of Packed Unsigned Byte Integers......Page 613
PMOVMSKB—Move Byte Mask......Page 616
PMULHUW—Multiply Packed Unsigned Integers and Store High Result......Page 618
PMULHW—Multiply Packed Signed Integers and Store High Result......Page 621
PMULLW—Multiply Packed Signed Integers and Store Low Result......Page 624
PMULUDQ—Multiply Packed Unsigned Doubleword Integers......Page 627
POP—Pop a Value from the Stack......Page 629
POPA/POPAD—Pop All General-Purpose Registers......Page 633
POPF/POPFD—Pop Stack into EFLAGS Register......Page 635
POR—Bitwise Logical OR......Page 638
PREFETCHh—Prefetch Data Into Caches......Page 640
PSADBW—Compute Sum of Absolute Differences......Page 642
PSHUFD—Shuffle Packed Doublewords......Page 645
PSHUFHW—Shuffle Packed High Words......Page 648
PSHUFLW—Shuffle Packed Low Words......Page 650
PSHUFW—Shuffle Packed Words......Page 652
PSLLDQ—Shift Double Quadword Left Logical......Page 654
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical......Page 655
PSRAW/PSRAD—Shift Packed Data Right Arithmetic......Page 660
PSRLDQ—Shift Double Quadword Right Logical......Page 664
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical......Page 665
PSUBB/PSUBW/PSUBD—Subtract Packed Integers......Page 670
PSUBQ—Subtract Packed Quadword Integers......Page 674
PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed Saturation......Page 676
PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers with Unsigned Saturation......Page 679
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data......Page 682
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ— Unpack Low Data......Page 686
PUSH—Push Word or Doubleword Onto the Stack......Page 690
PUSHA/PUSHAD—Push All General-Purpose Registers......Page 693
PUSHF/PUSHFD—Push EFLAGS Register onto the Stack......Page 695
PXOR—Logical Exclusive OR......Page 697
RCL/RCR/ROL/ROR-—Rotate......Page 699
RCPPS—Compute Reciprocals of Packed Single-Precision Floating-Point Values......Page 704
RCPSS—Compute Reciprocal of Scalar Single-Precision Floating- Point Values......Page 707
RDMSR—Read from Model Specific Register......Page 709
RDPMC—Read Performance-Monitoring Counters......Page 711
RDTSC—Read Time-Stamp Counter......Page 714
RDTSC—Read Time-Stamp Counter (Continued)......Page 715
REP/REPE/REPZ/REPNE /REPNZ—Repeat String Operation Prefix......Page 716
RET—Return from Procedure......Page 719
ROL/ROR—Rotate......Page 725
RSM—Resume from System Management Mode......Page 726
RSQRTPS—Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values......Page 727
RSQRTSS—Compute Reciprocal of Square Root of Scalar Single- Precision Floating-Point Value......Page 729
SAHF—Store AH into Flags......Page 731
SAL/SAR/SHL/SHR—Shift......Page 732
SBB—Integer Subtraction with Borrow......Page 736
SCAS/SCASB/SCASW/SCASD—Scan String......Page 738
SETcc—Set Byte on Condition......Page 741
SFENCE—Store Fence......Page 743
SGDT/SIDT—Store Global/Interrupt Descriptor Table Register......Page 744
SHL/SHR—Shift Instructions......Page 746
SHLD—Double Precision Shift Left......Page 747
SHRD—Double Precision Shift Right......Page 749
SHUFPD—Shuffle Packed Double-Precision Floating-Point Values......Page 751
SHUFPS—Shuffle Packed Single-Precision Floating-Point Values......Page 754
SIDT—Store Interrupt Descriptor Table Register......Page 757
SLDT—Store Local Descriptor Table Register......Page 758
SMSW—Store Machine Status Word......Page 760
SQRTPD—Compute Square Roots of Packed Double-Precision Floating-Point Values......Page 762
SQRTPS—Compute Square Roots of Packed Single-Precision Floating-Point Values......Page 764
SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value......Page 766
SQRTSS—Compute Square Root of Scalar Single-Precision Floating-Point Value......Page 768
STC—Set Carry Flag......Page 770
STD—Set Direction Flag......Page 771
STI—Set Interrupt Flag......Page 772
STMXCSR—Store MXCSR Register State......Page 774
STOS/STOSB/STOSW/STOSD—Store String......Page 776
STR—Store Task Register......Page 779
SUB—Subtract......Page 781
SUBPD—Subtract Packed Double-Precision Floating-Point Values......Page 783
SUBPS—Subtract Packed Single-Precision Floating-Point Values......Page 785
SUBSD—Subtract Scalar Double-Precision Floating-Point Values......Page 787
SUBSS—Subtract Scalar Single-Precision Floating-Point Values......Page 789
SYSENTER—Fast System Call......Page 791
SYSEXIT—Fast Return from Fast System Call......Page 795
TEST—Logical Compare......Page 798
UCOMISD—Unordered Compare Scalar Double-Precision Floating- Point Values and Set EFLAGS......Page 800
UCOMISS—Unordered Compare Scalar Single-Precision Floating- Point Values and Set EFLAGS......Page 803
UD2—Undefined Instruction......Page 806
UNPCKHPD—Unpack and Interleave High Packed Double- Precision Floating-Point Values......Page 807
UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values......Page 810
UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point Values......Page 813
UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values......Page 816
VERR, VERW—Verify a Segment for Reading or Writing......Page 819
WAIT/FWAIT—Wait......Page 821
WBINVD—Write Back and Invalidate Cache......Page 822
WRMSR—Write to Model Specific Register......Page 824
XADD—Exchange and Add......Page 826
XCHG—Exchange Register/Memory with Register......Page 828
XLAT/XLATB—Table Look-up Translation......Page 830
XOR—Logical Exclusive OR......Page 832
XORPD—Bitwise Logical XOR for Double-Precision Floating-Point Values......Page 834
XORPS—Bitwise Logical XOR for Single-Precision Floating-Point Values......Page 836
A.1.1. Codes for Addressing Method......Page 840
A.2. OPCODE LOOK-UP EXAMPLES......Page 842
A.2.2. Two-Byte Opcode Instructions......Page 843
A.2.3. Opcode Map Notes......Page 844
A.2.4. Opcode Extensions For One- And Two-byte Opcodes......Page 851
A.2.5.3. Escape Opcodes with D8 as First Byte......Page 853
A.2.5.4. Escape Opcodes with D9 as First Byte......Page 855
A.2.5.5. Escape Opcodes with DA as First Byte......Page 856
A.2.5.6. Escape Opcodes with DB as First Byte......Page 857
A.2.5.7. Escape Opcodes with DC as First Byte......Page 859
A.2.5.8. Escape Opcodes with DD as First Byte......Page 860
A.2.5.9. Escape Opcodes with DE as First Byte......Page 862
A.2.5.10. Escape Opcodes with DF As First Byte......Page 863
B.1. Machine Instruction Format......Page 868
B.1.1. Reg Field (reg)......Page 869
B.1.3. Sign Extend (s) Bit......Page 870
B.1.5. Special-Purpose Register (eee) Field......Page 871
B.1.7. Direction (d) Bit......Page 872
B.2. General-Purpose Instruction Formats and Encodings......Page 873
B.3.3. MMX Instruction Formats and Encodings Table......Page 886
B.4. P6 Family INstruction Formats and Encodings......Page 889
B.5. SSE Instruction Formats and Encodings......Page 890
B.6.1. Granularity Field (gg)......Page 898
B.7. Floating-Point Instruction Formats and Encodings......Page 911
APPENDIX C Intel C/C++ Compiler Intrinsics and Functional Equivalents......Page 920
C.1. Simple Intrinsics......Page 922
C.2. Composite Intrinsics......Page 950