Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation: 12th International Workshop, PATMOS 2002 Seville, Spain, September 11–13, 2002 Proceedings

The First Quartz Electronic Watch....Pages 1-15
An Improved Power Macro-Model for Arithmetic Datapath Components....Pages 16-24
Performance Comparison of VLSI Adders Using Logical Effort....Pages 25-34
MDSP: A High-Performance Low-Power DSP Architecture....Pages 35-44
Impact of Technology in Power-Grid-Induced Noise....Pages 45-54
Exploiting Metal Layer Characteristics for Low-Power Routing....Pages 55-64
Crosstalk Measurement Technique for CMOS ICs....Pages 65-70
Instrumentation Set-up for Instruction Level Power Modeling....Pages 71-80
Low-Power Asynchronous A/D Conversion....Pages 81-91
Optimal Two-Level Delay — Insensitive Implementation of Logic Functions....Pages 92-100
Resonant Multistage Charging of Dominant Capacitances....Pages 101-107
A New Methodology to Design Low-Power Asynchronous Circuits....Pages 108-117
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library....Pages 118-127
Clocking and Clocked Storage Elements in Multi-GHz Environment....Pages 128-145
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment....Pages 146-155
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping....Pages 156-166
Robust SAT-Based Search Algorithm for Leakage Power Reduction....Pages 167-177
PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI....Pages 178-187
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems....Pages 188-197
Clock Distribution Network Optimization under Self-Heating and Timing Constraints....Pages 198-208
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches....Pages 209-218
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers....Pages 219-228
Output Waveform Evaluation of Basic Pass Transistor Structure....Pages 229-238
An Approach to Energy Consumption Modeling in RC Ladder Circuits....Pages 239-246
Structure Independent Representation of Output Transition Time for CMOS Library....Pages 247-257
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors....Pages 258-267
Design and Realization of a Low Power Register File Using Energy Model....Pages 268-277
Register File Energy Reduction by Operand Data Reuse....Pages 278-288
Energy-Efficient Design of the Reorder Buffer....Pages 289-299
Trends in Ultralow-Voltage RAM Technology....Pages 300-313
Offine Data Profiling Techniques to Enhance Memory Compression in Embedded Systems....Pages 314-322
Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors....Pages 323-331
Power Consumption Estimation of a C Program for Data-Intensive Applications....Pages 332-341
A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission....Pages 342-352
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level....Pages 353-362
Low-Power FSMs in FPGA: Encoding Alternatives....Pages 363-370
Synthetic Generation of Events for Address-Event-Representation Communications....Pages 371-379
Reducing Energy Consumption via Low-Cost Value Prediction....Pages 380-389
Dynamic Voltage Scheduling for Real Time Asynchronous Systems....Pages 390-399
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level....Pages 400-408
Power Efficient Vector Quantization Design Using Pixel Truncation....Pages 409-418
Minimizing Spurious Switching Activities in CMOS Circuits....Pages 419-428
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates....Pages 429-437
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines....Pages 438-447
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters....Pages 448-457
Probabilistic Power Estimation for Digital Signal Processing Architectures....Pages 458-467
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input....Pages 468-476
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)....Pages 477-486
Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems....Pages 487-493