Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation: 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings

Front Matter....Pages -
A Quick Method for Energy Optimized Gate Sizing of Digital Circuits....Pages 1-10
Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures....Pages 11-21
A System Level Approach to Multi-core Thermal Sensors Calibration....Pages 22-31
Improving the Robustness of Self-timed SRAM to Variable Vdds....Pages 32-42
Architecture Extensions for Efficient Management of Scratch-Pad Memory....Pages 43-52
Pass Transistor Operation Modeling for Nanoscale Technologies....Pages 53-62
Timing Modeling of Flipflops Considering Aging Effects....Pages 63-72
Iterative Timing Analysis Considering Interdependency of Setup and Hold Times....Pages 73-82
Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology....Pages 83-91
Performance-Driven Clustering of Asynchronous Circuits....Pages 92-101
Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing....Pages 102-111
Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores....Pages 112-121
Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor Networks....Pages 122-132
Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs....Pages 133-142
Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique....Pages 143-151
NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode....Pages 152-161
An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs....Pages 162-172
Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution....Pages 173-179
Using Silent Writes in Low-Power Traffic-Aware ECC....Pages 180-192
SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging....Pages 193-203
Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization ....Pages 204-213
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating....Pages 214-225
A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts....Pages 226-236
Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits....Pages 237-246
C-elements for Hardened Self-timed Circuits....Pages 247-256
High-Speed and Low-Power PID Structures for Embedded Applications....Pages 257-266
Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits....Pages 267-277
Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels....Pages 278-287
Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study....Pages 288-297
A Framework for Architecture-Level Exploration of 3-D FPGA Platforms....Pages 298-307
Variability-Speed-Consumption Trade-off in Near Threshold Operation....Pages 308-316
High Level Synthesis of Asynchronous Circuits from Data Flow Graphs....Pages 317-330
A Secure D Flip-Flop against Side Channel Attacks....Pages 331-340
Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling....Pages 341-350
Back Matter....Pages -