High Performance Embedded Architectures and Compilers: Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings

Front Matter....Pages -
Keynote: Challenges on the Road to Exascale Computing....Pages 1-1
Keynote: Compilers in the Manycore Era....Pages 2-3
Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering....Pages 4-18
Predictive Runtime Code Scheduling for Heterogeneous Architectures....Pages 19-33
Collective Optimization....Pages 34-49
High Speed CPU Simulation Using LTU Dynamic Binary Translation....Pages 50-64
Integrated Modulo Scheduling for Clustered VLIW Architectures....Pages 65-79
Software Pipelining in Nested Loops with Prolog-Epilog Merging....Pages 80-94
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables....Pages 95-109
MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor....Pages 110-124
IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor....Pages 125-139
A Hardware Task Scheduler for Embedded Video Processing....Pages 140-152
Finding Stress Patterns in Microprocessor Workloads....Pages 153-167
Deriving Efficient Data Movement from Decoupled Access/Execute Specifications....Pages 168-182
MPSoC Design Using Application-Specific Architecturally Visible Communication....Pages 183-197
Communication Based Proactive Link Power Management....Pages 198-215
Mapping and Synchronizing Streaming Applications on Cell Processors....Pages 216-230
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors....Pages 231-247
Accomodating Diversity in CMPs with Heterogeneous Frequencies....Pages 248-262
A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip....Pages 263-277
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture....Pages 278-292
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines....Pages 293-307
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic....Pages 308-323
Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures....Pages 324-338
Revisiting Cache Block Superloading....Pages 339-354
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors....Pages 355-372
In-Network Caching for Chip Multiprocessors....Pages 373-388
Parallel LDPC Decoding on the Cell/B.E. Processor....Pages 389-403
Parallel H.264 Decoding on an Embedded Multicore Processor....Pages 404-418
Back Matter....Pages -