Field Programmable Logic and Application: 14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004. Proceedings

Front Matter....Pages -
FPGAs and the Era of Field Programmability....Pages 1-1
Reconfigurable Systems Emerge....Pages 2-11
System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?....Pages 12-12
Hardware Accelerated Novel Protein Identification....Pages 13-22
Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices....Pages 23-32
A Key Management Architecture for Securing Off-Chip Data Transfers....Pages 33-42
FPGA Implementation of Biometric Authentication System Based on Hand Geometry....Pages 43-53
SoftSONIC: A Customisable Modular Platform for Video Applications....Pages 54-63
Deploying Hardware Platforms for SoC Validation: An Industrial Case Study....Pages 64-73
Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes....Pages 74-83
Power Analysis Attacks Against FPGA Implementations of the DES....Pages 84-94
Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer....Pages 95-104
Stochastic Simulation for Biochemical Reactions on FPGA....Pages 105-114
Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures....Pages 115-124
Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine....Pages 125-134
Improving FPGA Performance and Area Using an Adaptive Logic Module....Pages 135-144
A Dual-V DD Low Power FPGA Architecture....Pages 145-157
Simultaneous Timing Driven Clustering and Placement for FPGAs....Pages 158-167
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis....Pages 168-178
Compact Buffered Routing Architecture....Pages 179-188
On Optimal Irregular Switch Box Designs....Pages 189-199
Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation....Pages 200-208
Comparative Study of SRT-Dividers in FPGA....Pages 209-220
Second Order Function Approximation Using a Single Multiplication on FPGAs....Pages 221-230
Efficient Modular Division Implementation....Pages 231-240
A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management....Pages 241-250
The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures....Pages 251-260
A High-Density Optically Reconfigurable Gate Array Using Dynamic Method....Pages 261-269
Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device....Pages 270-278
Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA....Pages 279-288
Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays....Pages 289-300
A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks....Pages 301-310
Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs....Pages 311-321
BIST Based Interconnect Fault Location for FPGAs....Pages 322-332
FPGAs BIST Evaluation....Pages 333-343
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor....Pages 344-353
Evaluating Fault Emulation on FPGA....Pages 354-363
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs....Pages 364-373
Multiple Restricted Multiplication....Pages 374-383
Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices....Pages 384-393
A Steerable Complex Wavelet Construction and Its Implementation on FPGA....Pages 394-403
Programmable Logic Has More Computational Power than Fixed Logic....Pages 404-413
JHDLBits: The Merging of Two Worlds....Pages 414-423
A System Level Resource Estimation Tool for FPGAs....Pages 424-433
The PowerPC Backend Molen Compiler....Pages 434-443
An Integrated Online Scheduling and Placement Methodology....Pages 444-453
On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities....Pages 454-463
Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor – An Approach to Tough Cases –....Pages 464-473
Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters....Pages 474-483
Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems....Pages 484-493
Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2....Pages 494-504
Three-Dimensional Dynamic Programming for Homology Search....Pages 505-515
An Instance-Specific Hardware Algorithm for Finding a Maximum Clique....Pages 516-525
IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter....Pages 526-535
Automatic Creation of Reconfigurable PALs/PLAs for SoC....Pages 536-545
A Key Agile 17.4 Gbit/sec Camellia Implementation....Pages 546-554
High Performance True Random Number Generator in Altera Stratix FPLDs....Pages 555-564
A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays....Pages 565-574
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation....Pages 575-585
Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor....Pages 586-595
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors....Pages 596-605
Storage Allocation for Diverse FPGA Memory Specifications....Pages 606-616
Real Time Optical Flow Processing System....Pages 617-626
Methods and Tools for High-Resolution Imaging....Pages 627-636
Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation....Pages 637-647
A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data....Pages 648-657
A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems....Pages 658-668
An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms....Pages 669-678
HW/SW Co-design by Automatic Embedding of Complex IP Cores....Pages 679-689
Increasing Pipelined IP Core Utilization in Process Networks Using Exploration....Pages 690-699
Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs....Pages 700-709
SOC and RTOS: Managing IPs and Tasks Communications....Pages 710-718
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays....Pages 719-728
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms....Pages 729-739
Power-Driven Design Partitioning....Pages 740-750
Power Consumption Reduction Through Dynamic Reconfiguration....Pages 751-760
The XPP Architecture and Its Co-simulation Within the Simulink Environment....Pages 761-770
An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer....Pages 771-780
Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration....Pages 781-790
Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS – High Energy Physics Experiment....Pages 791-800
Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs....Pages 801-810
SystemC for the Design and Modeling of Programmable Systems....Pages 811-820
An Evolvable Hardware Tutorial....Pages 821-830
A Runtime Environment for Reconfigurable Hardware Operating Systems....Pages 831-835
A Dynamically Reconfigurable Asynchronous FPGA Architecture....Pages 836-841
Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures....Pages 842-846
Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices....Pages 847-851
Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs....Pages 852-856
Automating the Layout of Reconfigurable Subsystems via Template Reduction....Pages 857-861
FPGA Acceleration of Rigid Molecule Interactions....Pages 862-867
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path....Pages 868-873
Exploring Potential Benefits of 3D FPGA Integration....Pages 874-880
System-Level Modeling of Dynamically Reconfigurable Co-processors....Pages 881-885
A Development Support System for Applications That Use Dynamically Reconfigurable Hardware....Pages 886-890
Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures....Pages 891-899
Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs....Pages 900-905
Mapping Basic Recursive Structures to Runtime Reconfigurable Hardware....Pages 906-910
Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA....Pages 911-916
Java Technology in an FPGA....Pages 917-921
Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers....Pages 922-926
The Chess Monster Hydra....Pages 927-932
FPGA-Efficient Hybrid LUT/CORDIC Architecture....Pages 933-937
A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays....Pages 938-942
Design and Implementation of a CFAR Processor for Target Detection....Pages 943-947
A Parallel FFT Architecture for FPGAs....Pages 948-953
FPGA Custom DSP for ECG Signal Analysis and Compression....Pages 954-958
FPGA Implementation of Adaptive Multiuser Detector for DS-CDMA Systems....Pages 959-964
Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design....Pages 965-969
A Low Power FPAA for Wide Band Applications....Pages 970-974
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs....Pages 975-979
Real-Time Computation of the Generalized Hough Transform....Pages 980-985
Minimum Sum of Absolute Differences Implementation in a Single FPGA Device....Pages 986-990
Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic....Pages 991-995
High Throughput Serpent Encryption Implementation....Pages 996-1000
Implementation of Elliptic Curve Cryptosystems over GF(2 $^{\\mbox{\\small n}}$ ) in Optimal Normal Basis on a Reconfigurable Computer....Pages 1001-1005
Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V....Pages 1006-1010
A Reconfigurable Communication Processor Compatible with Different Industrial Fieldbuses....Pages 1011-1016
Multithreading in a Hyper-programmable Platform for Networked Systems....Pages 1017-1021
An Environment for Exploring Data-Driven Architectures....Pages 1022-1026
FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T....Pages 1027-1031
A Dynamic NoC Approach for Communication in Reconfigurable Devices....Pages 1032-1036
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems....Pages 1037-1041
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications....Pages 1042-1046
A Structured Methodology for System-on-an-FPGA Design....Pages 1047-1051
Secure Logic Synthesis....Pages 1052-1056
Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion....Pages 1057-1061
The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead....Pages 1062-1066
Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory....Pages 1067-1072
FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat Head....Pages 1073-1075
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation....Pages 1076-1079
Processing Repetitive Sequence Structures with Mismatches at Streaming Rate....Pages 1080-1083
Artificial Neural Networks Processor – A Hardware Implementation Using a FPGA....Pages 1084-1086
FPGA Implementation of the Ridge Line Following Fingerprint Algorithm....Pages 1087-1089
A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals....Pages 1090-1092
Flow Monitoring in High-Speed Networks with 2D Hash Tables....Pages 1093-1097
A VHDL Generator for Elliptic Curve Cryptography....Pages 1098-1100
FPGA-Based Parallel Comparison of Run-Length-Encoded Strings....Pages 1101-1103
Real Environments Image Labelling Based on Reconfigurable Architectures....Pages 1104-1106
Object Oriented Programming Paradigms for the VHDL....Pages 1107-1109
Using Reconfigurable Hardware Through Web Services in Distributed Applications....Pages 1110-1112
Data Reuse in Configurable Architectures with RAM Blocks....Pages 1113-1115
A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development....Pages 1116-1118
AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits....Pages 1119-1123
A Self-Reconfiguration Framework for Multiprocessor CSoPCs....Pages 1124-1126
A Virtual File System for Dynamically Reconfigurable FPGAs....Pages 1127-1129
Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array....Pages 1130-1132
Design and Implementation of the Memory Scheduler for the PC-Based Router....Pages 1133-1135
Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach....Pages 1136-1138
Intellectual Property Protection for RNS Circuits on FPGAs....Pages 1139-1141
FPGA Implementation of a Tool Breakage Detection Algorithm in CNC Milling Machines....Pages 1142-1145
Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector....Pages 1146-1148
Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA....Pages 1149-1151
FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot....Pages 1152-1154
Real-Time Detection of Moving Objects....Pages 1155-1157
Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAs....Pages 1158-1161
Versatile Imaging Architecture Based on a System on Chip....Pages 1162-1164
A Hardware Implementation of a Content Based Image Retrieval Algorithm....Pages 1165-1167
Optimization Algorithms for Dynamic Reconfigurable Embedded Systems....Pages 1168-1168
Low Power Reconfigurable Devices....Pages 1169-1169
Code Re-ordering for a Class of Reconfigurable Microprocessors....Pages 1170-1170
Design Space Exploration for Distributed Hardware Reconfigurable Systems....Pages 1171-1171
TPR: Three-D Place and Route for FPGAs....Pages 1172-1172
Implementing Graphics Shaders Using FPGAs....Pages 1173-1173
Preemptive Hardware Task Management....Pages 1174-1174
Automated Speculation and Parallelism in High Performance Network Applications....Pages 1175-1175
Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems....Pages 1176-1177
A Specific Scheduling Flow for Dynamically Reconfigurable Hardware....Pages 1178-1179
Design and Evaluation of an FPGA Architecture for Software Protection....Pages 1180-1180
Scalable Defect Tolerance Beyond the SIA Roadmap....Pages 1181-1182
Run-Time Reconfiguration Management for Adaptive High-Performance Computing Systems....Pages 1183-1183
Optimized Field Programmable Gate Array Based Function Evaluation....Pages 1184-1184
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks....Pages 1185-1185
A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware....Pages 1186-1187
On Computing Maximum Likelihood Phylogeny Using FPGA....Pages 1188-1188
Minimising Reconfiguration Overheads in Embedded Applications (Abstract)....Pages 1189-1189
Application Specific Small-Scale Reconfigurability....Pages 1190-1190
Efficient FPGA-Based Security Kernels....Pages 1191-1191
Back Matter....Pages -