Ferroelectric-Gate Field Effect Transistor Memories: Device Physics and Applications (Topics in Applied Physics, 131)

Preface
Contents
Contributors
Part I Introduction
1 Features, Principles, and Developments of Ferroelectric-Gate Field-Effect Transistors
	1.1 Background of Ferroelectric Memories
		1.1.1 Historical Background
		1.1.2 Classification of Nonvolatile Ferroelectric Memories
	1.2 Degradation and Improvement of Memorized States in MFIS Structures
		1.2.1 Degradation of Memorized States
		1.2.2 Theoretical Analysis of the Band Profile and Retention Degradation of MFIS Capacitors
		1.2.3 Calculated Time Dependences of Band Profile and Capacitance of the MFIS Structure
		1.2.4 Effects of Currents Through the Ferroelectric and Insulator Layers on the Retention Characteristics of the MFIS Structure
		1.2.5 Methods for Suppressing Leakage Current Through the MFIS Structure
		1.2.6 Retention Improvement by Heat and Radical Treatments
	1.3 Improvement of Ferroelectric-Gate FETs
	1.4 Conclusion
	References
Part II Practical Characteristics of Inorganic Ferroelectric-Gate FETs: Si-Based Ferroelectric-Gate Field Effect Transistors
2 Development of High-Endurance and Long-Retention FeFETs of Pt/CaySr1−yBi2Ta2O9/(HfO2)x(Al2O3)1−x/Si Gate Stacks
	2.1 Introduction
	2.2 Basic Fabrication Process and Characterization of Pt/SBT/HAO/Si FeFETs
		2.2.1 Fabrication Process
		2.2.2 Static Memory Window
		2.2.3 Retention
		2.2.4 Endurance
		2.2.5 Writing Speed
		2.2.6 Id–Vg and Retention at Elevated Temperatures
	2.3 Requirements to the Layers in MFIS
		2.3.1 Requirements to the Layers M, F, I
		2.3.2 Requirements Especially to the I-and-IL Layers
		2.3.3 Requirements to the F Layer
	2.4 Preparation of HAO for Pt/SBT/HAO/Si Gate Stack
		2.4.1 Single HAO(x) and the MIS Characters at Various Composition Ratios
		2.4.2 Comparison of O2 and N2 Ambient in Depositing HAO
		2.4.3 Effect of N2 Ambient Pressure Increase in Depositing HAO
	2.5 Nitriding and Oxinitriding Si of MFIS FeFET
		2.5.1 Direct Nitriding Si for Large Memory Window of FeFET
		2.5.2 Oxinitriding Si for Improving the Si Interface of FeFET
	2.6 Using CSBT Instead of SBT in FeFET
	2.7 Summary
	References
3 Downsizing of High-Endurance and Long-Retention Pt/CaySr1−yBi2Ta2O9/(HfO2)x(Al2O3)1−x/Si FeFETs
	3.1 Introduction
	3.2 Downsizing Process of CSBT-Based FeFETs
		3.2.1 2 μm ≤ L < 10 μm
		3.2.2 0.26 μm ≤ L < 1 μm
		3.2.3 0.1 μm ≤ L < 0.2 μm
	3.3 Summary
	References
4 Nonvolatile Field-Effect Transistors Using Ferroelectric-Doped HfO2 Films
	4.1 Introduction
	4.2 FeFET Integration
		4.2.1 Ferroelectric-Doped HfO2
		4.2.2 Si-Doped HfO2
		4.2.3 Other Doped HfO2
	4.3 Memory Properties of Ferroelectric Hafnium Oxide
	4.4 Hafnium Oxide-Based Ferroelectric Field-Effect Transistor
		4.4.1 Device Performance
		4.4.2 Device Reliability
	4.5 Summary and Outlook
	References
5 Switching in Nanoscale Hafnium Oxide-Based Ferroelectric Transistors
	5.1 Introduction
	5.2 Experimental Section
	5.3 Abrupt Switching
	5.4 Stochastic Switching
	5.5 Accumulative Switching
	5.6 Conclusions
	References
Part III Practical Characteristics of Inorganic Ferroelectric-Gate FETs: Thin Film-Based Ferroelectric-Gate Field Effect Transistors
6 Oxide-Channel Ferroelectric-Gate Thin-Film Transistors with Nonvolatile Memory Function
	6.1 Introduction
	6.2 Features of Ferroelectric-Gate Insulator
	6.3 Charge Density of ITO-Channel FGTs
	6.4 Electrical Properties of ITO-Channel FGTs
	6.5 Transparent ITO/BLT FGT
	6.6 ITO-Channel TFTs with High-k Gate Insulator
	6.7 Conclusions
	References
7 ZnO/Pb(Zr,Ti)O3 Gate Structure Ferroelectric FETs
	7.1 Introduction
	7.2 Experimental Procedure
	7.3 Device Characteristics and Discussions
		7.3.1 Basic Characteristics
		7.3.2 Correlated Motion Dynamics of Electron Channels and Domain Walls
		7.3.3 60-nm-Channel-Length FeFET
	7.4 Summary
	References
8 Novel Ferroelectric Gate Field-Effect Transistors (FeFETs); Controlled Polarization-Type FeFETs
	8.1 Introduction
		8.1.1 Field-Effect Control of Carrier Concentration
		8.1.2 Ferroelectric Field Effect
	8.2 Fabrication and Properties of CP-Type FeTFTs
		8.2.1 Bottom-Gate-Type TFTs (1-a in Fig. 8.1)
		8.2.2 Impedance Analysis of Channel Conduction Underneath the Bottom-Ferroelectric-Gate Using an RC Lumped Constant Circuit
		8.2.3 Top-Gate-Type TFTs (2-B in Fig. 8.1)
	8.3 Effect of Spontaneous Polarization of the Polar Semiconductor on the Electronic Structure of the Poly(Vinylidene Fluoride–Trifluoroethylene)/ZnO Heterostructures
	8.4 Conclusions
	References
Part IV Practical Characteristics of Organic Ferroelectric-Gate FETs: Si-Based Ferroelectric-Gate Field Effect Transistors
9 Nonvolatile Ferroelectric Memory Transistors Using PVDF, P(VDF-TrFE) and Blended PVDF/P(VDF-TrFE)  Thin Films
	9.1 Introduction of Nonvolatile Ferroelectric Memory Transistors
	9.2 Experimental Procedure
	9.3 Results and Discussion
		9.3.1 Electrical Properties of Poly(Vinylidene) (PVDF) Thin Film
		9.3.2 Electrical Properties of MFSFETs with PVDF Thin Film
		9.3.3 Electrical Properties of MFSFETs with PVDF-TrFE Thin Film
		9.3.4 Electrical Properties of FeFETs with Blended PVDF/P(VDF-TrFE) Thin Film
	9.4 Conclusion
	References
10 Poly(Vinylidenefluoride-Trifluoroethylene) P(VDF-TrFE)/Semiconductor Structure Ferroelectric-Gate FETs
	10.1 Introduction
		10.1.1 Problem of Oxide/Silicon-Based FeFETs
		10.1.2 Property of Organic Ferroelectric Material; P(VDF-TrFE)
	10.2 Ferroelectric Properties of VDF Base Polymers
		10.2.1 Ferroelectricity of PVDF
		10.2.2 Items that Should Be Solved Before Application
		10.2.3 Ferroelectricity of Random Copolymer P(VDF-TrFE)
	10.3 Ferroelectric P(VDF-TrFE) Gate FeFETs
		10.3.1 FeFETs Using Inorganic Semiconductors
		10.3.2 FeFETs Using Organic Semiconductors
	10.4 Summary
	References
Part V Practical Characteristics of Organic Ferroelectric-Gate FETs: Thin Film-Based Ferroelectric-Gate Field Effect Transistors
11 P(VDF-TeFE)/Organic Semiconductor Structure Ferroelectric-Gate FETs
	11.1 Introduction
		11.1.1 Organic Ferroelectric-Gate FETs
		11.1.2 PVDF-TeFE Organic Ferroelectrics
		11.1.3 Organic Semiconductors
	11.2 Experimental Procedure
		11.2.1 Preparation of P(VDF-TeFE) Thin Films
		11.2.2 Preparation of Organic Semiconductors
		11.2.3 Preparation and Characterization Methods  for Ferroelectric-Gate FETs
	11.3 Results and Discussion
		11.3.1 Basic Properties of Fabricated P(VDF-TeFE)  Thin Films
		11.3.2 Basic Properties of Pentacene and Rubrene Semiconductors
		11.3.3 P(VDF-TeFE)/pentacene Ferroelectric-Gate FETs
		11.3.4 P(VDF-TeFE)/rubrene Ferroelectric-Gate FETs
	11.4 Conclusions
	References
12 Nonvolatile Ferroelectric Memory Thin-Film Transistors Using a Poly(Vinylidene Fluoride Trifluoroethylene) Gate Insulator and an Oxide Semiconductor Active Channel
	12.1 Introduction
	12.2 Choice of Materials
		12.2.1 Organic Ferroelectric Gate Insulators
		12.2.2 Oxide Semiconductor Active Channels
	12.3 Design of Device Structures
		12.3.1 Design Schemes for Device Operations [26]
		12.3.2 Typical Device Structure and Characteristics
	12.4 Process Optimization
		12.4.1 Lithography Compatible Patterning Process
		12.4.2 Interface Protection Layer
		12.4.3 Oxide Channel Solution Process
	12.5 Promising Applications
		12.5.1 Nonvolatile Flexible Memory
		12.5.2 Nonvolatile Transparent Memory
		12.5.3 Low-Power Backplane Device for Display Panel
		12.5.4 Other Feasible Applications
	12.6 Memory Array Integration
		12.6.1 Memory Cell Integration Process
		12.6.2 Disturb-Free Memory Cell Array
	12.7 Remaining Technical Issues
		12.7.1 Low-Voltage Operation
		12.7.2 Turn-on Voltage Control
		12.7.3 Program Speed
		12.7.4 Data Retention
	12.8 Conclusions and Outlooks
	References
Part VI Practical Characteristics of Organic Ferroelectric-Gate FETs: Ferroelectric-Gate Field Effect Transistors with Flexible Substrates
13 Mechanically Flexible Nonvolatile Field Effect Transistor Memories with Ferroelectric Polymers
	13.1 Introduction
	13.2 FeFETs with Ferroelectric Polymers
		13.2.1 Ferroelectric Polymers
		13.2.2 Operation Principle of FeFETs
	13.3 FeFET on Flexible Substrates
		13.3.1 Flexible FeFETs with Inorganic Semiconductors
		13.3.2 Flexible FeFETs with Low Molecule Organic Semiconductors
		13.3.3 Flexible FeFETs with Polymer Semiconductors
	13.4 Characterization of Mechanical Properties of a Flexible FeFET
		13.4.1 Bending Characteristics
		13.4.2 Nano-indentation
		13.4.3 Nano-scratch
	13.5 Conclusions
	References
14 Paper Transistors with Organic Ferroelectric P(VDF-TrFE) Thin Films Using a Solution Processing Method
	14.1 Introduction
	14.2 Experimental Procedure
	14.3 Results and Discussion
		14.3.1 P(VDF-TrFE)/Al/Paper Structures
		14.3.2 P3HT/PVDF-TrFE/Al/Paper Structures
	14.4 Conclusion
	References
15 Non-volatile Organic Ferroelectric Field-Effect Transistors Fabricated on Al Foil and Polyimide Substrates
	15.1 Ultra-flexible Non-volatile Organic Ferroelectric Field-Effect Transistors
	15.2 Experimental Procedure
	15.3 Results and Discussion
		15.3.1 Characteristics of Ultra-Flexible FeFETs on Polyimide
		15.3.2 Organic Field-Effect Transistors Fabricated on Al Foil Substrates
	15.4 Conclusion
	References
16 Novel Application of FeFETs to NAND Flash Memory Circuits
	16.1 Introduction
	16.2 Fabrication Process
	16.3 Test Element Group Characteristics
		16.3.1 Single-Cell Performance
		16.3.2 Logic Element Performance: NOT Gates and a Ring Oscillator
		16.3.3 Test Circuits for Block Selector and Bit-Line Selector
		16.3.4 Single-Cell Self-boost Operations Using a 4 × 2 Miniature Array
	16.4 64 kb Fe-NAND Flash Memory
		16.4.1 Architecture
		16.4.2 Basic Operations
		16.4.3 Results and Discussion
	16.5 Conclusion
	References
17 Novel Applications of Antiferroelectrics and Relaxor Ferroelectrics: A Material’s Point of View
	17.1 Introduction
	17.2 Electrostatic Supercapacitors
	17.3 Electrocaloric Cooling
	17.4 Pyroelectric Energy Harvesting
	17.5 IR Sensing
	17.6 Perspectives
	17.7 Conclusions
	References
18 Polymorphism of Hafnia-Based Ferroelectrics for Ferroelectric Field-Effect Transistors
	18.1 Thermodynamic Stabilization of the Pca21 Orthorhombic Phase
		18.1.1 Effects of Dopants
		18.1.2 Surface/Interface/Grain Boundary Energy Effects
		18.1.3 Effects of the Film Stress and Upper Capping Layer
	18.2 Kinetic Mechanism
	18.3 Conclusion
	References
19 Adaptive-Learning Synaptic Devices Using Ferroelectric-Gate Field-Effect Transistors for Neuromorphic Applications
	19.1 Introduction
	19.2 Operation Principles of Adaptive-Learning  Neuron Circuits
		19.2.1 Pulse Frequency Modulation-Type Ferroelectric Synaptic Device Operations
		19.2.2 Multiple-Input Neuron Circuit and Electrically Modifiable Synapse Array
	19.3 Fundamental Characteristics of Ferroelectric  Synapse FETs
		19.3.1 Fundamental Characteristics of Ferroelectric SrBi2Ta2O9 (SBT) Thin Films
		19.3.2 Basic Device Characteristics of MFSFETs
	19.4 Electrically Modifiable Synapse Array Using MFSFET
		19.4.1 Device Design of Ferroelectric Synapse Array
		19.4.2 Fabrication Process
		19.4.3 Weighted-Sum Operation of Synapse Array
	19.5 Adaptive-Learning Neuron Circuit Composed of an MFSFET and a CUJT Oscillation Circuit
		19.5.1 Device Design and Circuit Layout
		19.5.2 Adaptive-Learning Function of Ferroelectric  Neuron Circuit
	19.6 Improvement of Output Characteristics in Ferroelectric Neuron Circuit Using CMOS Schmitt-Trigger Oscillator
		19.6.1 Device and Circuit Designs
		19.6.2 Adaptive-Learning Functions with Improved Output Characteristics
	19.7 Improvement of Memory Retention in Ferroelectric Neuron Circuit Using MFMIS-Structured Synapse Device
		19.7.1 Device Designs for MFMIS Synapse Device
		19.7.2 Adaptive-Learning Functions with Improved Memory Retention Characteristic
	19.8 Conclusions and Outlooks
	References
20 FeFETs for Neuromorphic Systems
	20.1 Introduction
	20.2 FeFETs for Spiking Neural Networks
		20.2.1 FeFET as a Neuron
		20.2.2 FeFET as a Synapse
	20.3 FeFETs for Deep Neural Networks
	20.4 Conclusions
	References
21 Applications of Oxide-Channel Ferroelectric-Gate Thin-Film Transistors
	21.1 Introduction
	21.2 Memory Circuit Application Using Ferroelectric-Gate Transistors
	21.3 Fabrication of NAND Memory Cell Arrays Using Oxide-Channel Ferroelectric-Gate Transistors with 2-Tr Memory Cell Configuration
	21.4 Solution Process for Oxide-Channel Ferroelectric-Gate Transistors
		21.4.1 All-Oxide Ferroelectric-Gate TFTs  by Total Solution Process
		21.4.2 Fabrication of Oxide-Channel Ferroelectric-Gate TFTs by Nano-rheology Printing (n-RP)
	21.5 Summary and Conclusion
	References