ESD : RF Technology and Circuits

ESD......Page 4
Contents......Page 10
Preface......Page 18
Acknowledgements......Page 24
1.1 Fundamental Concepts of ESD Design......Page 26
1.2 Fundamental Concepts of RF ESD Design......Page 29
1.3 Key RF ESD Contributions......Page 35
1.5 ESD Failure Mechanisms......Page 38
1.5.1 RF CMOS ESD Failure Mechanisms......Page 39
1.5.3 Silicon Germanium Carbon ESD Failure Mechanisms in Silicon Germanium Carbon Devices......Page 40
1.5.5 Indium Gallium Arsenide ESD Failure Mechanisms......Page 41
1.6 RF Basics......Page 42
1.7.1 Z-Parameters......Page 46
1.7.3. S-Parameters......Page 47
1.7.4 T-Parameters......Page 48
1.8 Stability: RF Design Stability and ESD......Page 49
1.9.1 ESD-Induced D.C. Parameter Shift and Failure Criteria......Page 51
1.9.2 RF Parameters, ESD Degradation, and Failure Criteria......Page 53
1.10.1 ESD Testing Models......Page 54
1.10.2 RF Maximum Power-to-Failure and ESD Pulse Testing Methodology......Page 58
1.10.3 ESD-Induced RF Degradation and S-Parameter Evaluation Test Methodology......Page 62
1.11 Time Domain Reflectometry (TDR) and Impedance Methodology for ESD Testing......Page 64
1.11.1 Time Domain Reflectometry (TDR) ESD Test System Evaluation......Page 65
1.11.2 ESD Degradation System Level Method – Eye Tests......Page 69
1.12 Product Level ESD Test and RF Functional Parameter Failure......Page 71
1.13 Combined RF and ESD TLP Test Systems......Page 73
1.14 Closing Comments and Summary......Page 76
Problems......Page 77
References......Page 78
2.1.1 Ideal ESD Networks and the Current–Voltage d.c. Design Window......Page 86
2.1.2 Ideal ESD Networks in the Frequency Domain Design Window......Page 88
2.2 RF ESD Design Methods: Linearity......Page 89
2.3 RF ESD Design: Passive Element Quality Factors and Figures of Merit......Page 93
2.4 RF ESD Design Methods: Method of Substitution......Page 95
2.4.1 Method of Substitution of Passive Element to ESD Network Element......Page 96
2.4.2 Substitution of ESD Network Element to Passive Element......Page 97
2.5 RF ESD Design Methods: Matching Networks and RF ESD Networks......Page 98
2.5.1 RF ESD Method – Conversion of Matching Networks to ESD Networks......Page 99
2.5.2.1 Conversion of ESD Networks into L-Match Networks......Page 101
2.5.2.2 Conversion of ESD Networks into Pie-Match Networks......Page 102
2.5.2.3 Conversion of ESD Networks into T-Match Networks......Page 103
2.6 RF ESD Design Methods: Inductive Shunt......Page 104
2.7.1 Quality Factors and the Cancellation Method......Page 107
2.7.2 Inductive Cancellation of Capacitance Load and Figures of Merit......Page 108
2.7.3 Cancellation Method and ESD Circuitry......Page 110
2.8 RF ESD Design Methods: Impedance Isolation Technique Using LC Resonator......Page 114
2.9 RF ESD Design Methods: Lumped versus Distributed Loads......Page 116
2.9.1 RF ESD Distributed Load with Coplanar Wave Guides......Page 117
2.9.2 RF ESD Distribution Coplanar Waveguides Analysis Using ABCD Matrices......Page 118
2.10 ESD RF Design Synthesis and Floor Planning: RF, Analog, and Digital Integration......Page 120
2.10.1 ESD Power Clamp Placement Within a Domain......Page 121
2.10.2 Power Bus Architecture and ESD Design Synthesis......Page 122
2.10.3 VDD-to-VSS Power Rail Protection......Page 123
2.10.4 VDD-to-Analog VDD and VDD-to-RF VCC Power Rail Protection......Page 124
2.10.5 Interdomain ESD Protection Networks......Page 125
2.11 ESD Circuits and RF Bond Pad Integration......Page 126
2.12 ESD Structures Under Wire Bond Pads......Page 128
Problems......Page 131
References......Page 133
3.1 RF CMOS: ESD Device Comparisons......Page 136
3.2 Circular RF ESD Devices......Page 141
3.3 RF ESD Design—ESD Wiring Design......Page 143
3.4 RF Passives: ESD and Schottky Barrier Diodes......Page 145
3.5 RF Passives: ESD and Inductors......Page 147
3.6 RF Passives: ESD and Capacitors......Page 152
3.6.2 Varactors and Hyper-Abrupt Junction Varactor Capacitors......Page 153
3.6.3 Metal-ILD-Metal Capacitors......Page 154
3.6.4 Vertical Parallel Plate (VPP) Capacitors......Page 155
3.7 Summary and Closing Comments......Page 156
Problems......Page 157
References......Page 158
4.1.1 RF CMOS ESD Diode Networks......Page 164
4.1.2 RF CMOS Diode String ESD Network......Page 168
4.2 RF CMOS: Diode–Inductor ESD Networks......Page 170
4.2.1 RF Inductor–Diode ESD Networks......Page 172
4.2.2 RF Diode–Inductor ESD Networks......Page 173
4.3 RF CMOS Impedance Isolation LC Resonator ESD Networks......Page 174
4.3.2 RF CMOS Diode–LC ESD Networks......Page 175
4.3.3 Experimental Results of the RF CMOS LC–Diode Networks......Page 176
4.4 RF CMOS LNA ESD Design......Page 177
4.4.1 RF LNA ESD Design: Low Resistance ESD Inductor and ESD Diode Clamping Elements in Pie-Configuration......Page 178
4.5 RF CMOS T-Coil Inductor ESD Input Network......Page 182
4.6.1 RF CMOS Distributed RF ESD Networks......Page 184
4.6.2 RF CMOS Distributed RF ESD Networks using Series Inductor and Dual-Diode Shunt......Page 185
4.6.3 RF CMOS Distributed RF ESD Networks using Series Inductor and MOSFET Parallel Shunt......Page 188
4.7 RF CMOS Distributed ESD Networks: Transmission Lines and Coplanar Waveguides......Page 190
4.8 RF CMOS: ESD and RF LDMOS Power Technology......Page 192
4.9 RF CMOS ESD Power Clamps......Page 195
4.9.1 RC-Triggered MOSFET ESD Power Clamp......Page 197
4.9.2 High Voltage RC-Triggered MOSFET ESD Power Clamp......Page 199
4.9.3 Voltage-Triggered MOSFET ESD Power Clamps......Page 200
4.10 Summary and Closing Comments......Page 201
Problems......Page 202
References......Page 203
5.1.1 Bipolar Transistor Current Equations......Page 208
5.1.2 Bipolar Current Gain and Collector-to-Emitter Transport......Page 209
5.1.3 Unity Current Gain Cutoff Frequency......Page 210
5.2.1 Avalanche Multiplication and Breakdown......Page 211
5.2.2 Bipolar Transistor Breakdown......Page 213
5.3 Kirk Effect......Page 215
5.4.1 Voltage–Frequency Relationship......Page 216
5.4.2 Johnson Limit Current–Frequency Formulation......Page 218
5.4.3 Johnson Limit Power Formulation......Page 219
5.5 RF Instability: Emitter Collapse......Page 220
5.6 ESD RF Design Layout: Emitter, Base, and Collector Configurations......Page 226
5.7 ESD RF Design Layout: Utilization of a Second Emitter (Phantom Emitter)......Page 229
5.8 ESD RF Design Layout: Emitter Ballasting......Page 233
5.9 ESD RF Design Layout: Thermal Shunts and Thermal Lenses......Page 235
5.10 Base-Ballasting and RF Stability......Page 236
Problems......Page 238
References......Page 307
6.1 Heterojunctions and Silicon Germanium Technology......Page 242
6.1.1 Silicon Germanium HBT Devices......Page 243
6.1.2 Silicon Germanium Device Structure......Page 244
6.2 Silicon Germanium Physics......Page 246
6.3 Silicon Germanium Carbon......Page 249
6.4 Silicon Germanium ESD Measurements......Page 251
6.4.1 Silicon Germanium Collector-to-Emitter ESD Stress......Page 252
6.4.2 ESD Comparison of Silicon Germanium HBT and Silicon BJT......Page 254
6.4.3 SiGe HBT Electrothermal Human Body Model (HBM) Simulation of Collector–Emitter Stress......Page 257
6.5 Silicon Germanium Carbon Collector–Emitter ESD Measurements......Page 258
6.6 Silicon Germanium Transistor Emitter–Base Design......Page 262
6.6.1 Epitaxial-Base Heterojunction Bipolar Transistor (HBT) Emitter–Base Design......Page 263
6.6.3 SiGe HBT Emitter–Base Resistance Model......Page 265
6.6.4 SiGe HBT Emitter–Base Design and Silicide Placement......Page 266
6.6.5 Self-Aligned (SA) Emitter–Base Design......Page 270
6.6.6 Non-self aligned (NSA) Emitter–Base Design......Page 273
6.6.6.1 NSA Human Body Model (HBM) Step Stress......Page 274
6.6.6.2 Transmission line pulse (TLP) step stress......Page 275
6.6.6.3 RF Testing of SiGe HBT Emitter–Base Configuration......Page 276
6.6.6.4 Unity current gain cutoff frequency–collector current plots......Page 279
6.6.7 Silicon Germanium Carbon – ESD-Induced S-Parameter Degradation......Page 281
6.6.8 Electrothermal Simulation of Emitter–Base Stress......Page 283
6.7 Field-Oxide (FOX) Isolation Defined Silicon Germanium Heterojunction Bipolar Transistor HBM Data......Page 284
6.8 Silicon Germanium HBT Multiple-Emitter Study......Page 285
Problems......Page 287
References......Page 288
7.2 Gallium Arsenide Energy-to-Failure and Power-to-Failure......Page 294
7.3 Gallium Arsenide ESD Failures in Active and Passive Elements......Page 297
7.4 Gallium Arsenide HBT Devices and ESD......Page 298
7.4.1 Gallium Arsenide HBT Device ESD Results......Page 299
7.4.2 Gallium Arsenide HBT Diode Strings......Page 300
7.5.1 GaAs HBT Base–Collector Varactor......Page 302
7.7 Indium Gallium Arsenide and ESD......Page 304
Problems......Page 306
8.1 Bipolar Receivers and ESD......Page 312
8.2 Single Ended Common-Emitter Receiver Circuits......Page 313
8.2.1 Single-Ended Bipolar Receiver with D.C. Blocking Capacitors......Page 314
8.2.2 Single-Ended Bipolar Receiver with D.C. Blocking Capacitors and ESD Protection......Page 315
8.2.3.1 Bipolar Single-Ended Common-Emitter Circuit with Resistor Feedback Element......Page 316
8.2.3.2 Bipolar Single-Ended Common-Emitter Receiver  Circuit with Resistor–Capacitor Feedback Element......Page 317
8.2.4 Bipolar Single-Ended Common-Emitter Receiver Circuit with Emitter Degeneration......Page 318
8.2.5 Bipolar Single-Ended Common Emitter Circuit with Balun Output......Page 322
8.2.6 Bipolar Single-Ended Series Cascode Receiver Circuits......Page 323
8.3 Bipolar Differential Receiver Circuits......Page 325
8.3.1 Bipolar Differential Cascode Common-Emitter Receiver Circuits......Page 327
8.4 Bipolar ESD Input Circuits......Page 328
8.4.1 Diode-Configured Bipolar ESD Input Circuits......Page 332
8.4.2 Bipolar ESD Input: Resistor Grounded Base Bipolar ESD Input......Page 333
8.5.2 Zener Breakdown Voltage-Triggered ESD Power Clamps......Page 337
8.5.3 BVCEO Voltage-Triggered ESD Power Clamps......Page 343
8.5.4 Mixed Voltage Interface Forward-Bias Voltage and BVCEO-Breakdown Synthesized Bipolar ESD Power Clamps......Page 348
8.5.5 Ultra-Low Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamps......Page 353
8.5.6 Capacitively-Triggered BiCMOS ESD Power Clamps......Page 357
8.6 Bipolar ESD Diode String and Triple-Well Power Clamps......Page 359
Problems......Page 360
References......Page 362
9.1.1 Electrostatic Discharge and Radio Frequency (RF) Cosynthesis Design Methods......Page 364
9.1.2 ESD Hierarchical Pcell Physical Layout Generation......Page 365
9.2 ESD Design with Hierarchical Parameterized Cells......Page 366
9.2.1 Hierarchical Pcell Graphical Method......Page 367
9.2.2 Hierarchical Pcell Schematic Method......Page 369
9.3 ESD Design of RF CMOS-Based Hierarchical Parameterized Cells......Page 372
9.4 RF BiCMOS ESD Hierarchical Parameterized Cell......Page 374
9.4.1 BiCMOS ESD Input Networks......Page 375
9.4.2 BiCMOS ESD Rail-to-Rail......Page 378
9.4.3 BiCMOS ESD Power Clamps......Page 379
9.5 Advantages and Limitations of the RF ESD Design System......Page 384
9.6.1 Guard Rings for Internal and External Latchup Phenomena......Page 387
9.6.2 Guard Ring Theory......Page 388
9.6.3 Guard Ring Design......Page 390
9.6.4 Guard Ring Characterization......Page 392
Problems......Page 395
References......Page 396
10.1 Spark Gaps......Page 400
10.2.1 Field Emission Device (FED) as ESD Protection......Page 403
10.2.2 Field Emission Device in Gallium Arsenide Technology......Page 404
10.2.4 Field Emission Device Multiemitter ESD Design......Page 405
10.3 Off-Chip Protection and Off-Chip Transient Suppression Devices......Page 407
10.3.1 Off-Chip Transient Voltage Suppression (TVS) Devices......Page 408
10.3.2 Off-Chip Polymer Voltage Suppression (PVS) Devices......Page 409
10.4 Package-Level Mechanical ESD Solutions......Page 411
10.5 RF Proximity Communications Chip-to-Chip ESD Design Practices......Page 412
10.6 Summary and Closing Comments......Page 413
References......Page 414
Index......Page 416