Embedded Systems Design using the MSP430FR2355 LaunchPad™

Preface
	Why Another Book on Embedded Systems?
	How to Use This Book
	Additional Resources
Acknowledgments
Acknowledgments
Contents
1: Introduction to Embedded Systems
	1.1 What Is an Embedded System?
		Concept Check
2: Digital Logic Basics
	2.1 Number Systems
		2.1.1 Positional Number Systems
			2.1.1.1 Generic Structure
			2.1.1.2 Decimal Number System (Base 10)
			2.1.1.3 Binary Number System (Base 2)
			2.1.1.4 Hexadecimal Number System (Base 16)
				Concept Check
		2.1.2 Base Conversion
			2.1.2.1 Converting to Decimal
			2.1.2.2 Converting from Decimal
			2.1.2.3 Converting Between 2n Bases
				Concept Check
		2.1.3 Binary Arithmetic
			2.1.3.1 Addition (Carries)
			2.1.3.2 Subtraction (Borrows)
				Concept Check
		2.1.4 Unsigned and Signed Numbers
			2.1.4.1 Unsigned Numbers
			2.1.4.2 Signed Numbers (Two´s Complement)
			2.1.4.3 Arithmetic with Two´s Complement
				Concept Check
	2.2 Combinational Logic
		2.2.1 Basic Gates
			Concept Check
		2.2.2 Boolean Algebra
			Concept Check
		2.2.3 Combinational Logic Synthesis
			2.2.3.1 Canonical Sum of Products
			2.2.3.2 Canonical Product of Sums
			2.2.3.3 Logic Minimization in SOP Form
			2.2.3.4 Logic Minimization in POS Form
			2.2.3.5 Don´t Cares
			2.2.3.6 Identifying XOR Gates in K-maps
				Concept Check
		2.2.4 MSI Logic
			2.2.4.1 Decoders
			2.2.4.2 Encoders
			2.2.4.3 Multiplexers
			2.2.4.4 Demultiplexers
			2.2.4.5 Adders
			2.2.4.6 Subtractors
				Concept Check
	2.3 Sequential Logic
		2.3.1 Sequential Logic Storage Devices
			2.3.1.1 The Cross-Coupled Inverter Pair
			2.3.1.2 The SR Latch
			2.3.1.3 The S′R′ Latch
			2.3.1.4 SR Latch with Enable
			2.3.1.5 The D-Latch
			2.3.1.6 The D-Flip-Flop
			2.3.1.7 Registers
				Concept Check
		2.3.2 Finite State Machines
			2.3.2.1 Describing the Functionality of a FSM
			2.3.2.2 State Diagrams
			2.3.2.3 State Transition Tables
			2.3.2.4 Logic Synthesis for a FSM
			2.3.2.5 State Memory
			2.3.2.6 Next State Logic
			2.3.2.7 Output Logic
			2.3.2.8 The Final Logic Diagram
			2.3.2.9 FSM Design Process Overview
			2.3.2.10 FSM Design Example: Simple Control Unit
			2.3.2.11 FSM Design Example: 2-Bit Up Counter
			2.3.2.12 FSM Design Example: 2-Bit Binary Up/Down Counter
				Concept Check
	2.4 Memory
		2.4.1 Memory Terminology
			Concept Check
		2.4.2 Memory Architecture
			Concept Check
		2.4.3 Memory Technologies
			2.4.3.1 Masked Read Only Memory (MROM)
			2.4.3.2 Programmable Read Only Memory (PROM)
			2.4.3.3 Erasable Programmable Read Only Memory (EPROM)
			2.4.3.4 Electrically Erasable Programmable Read Only Memory (EEPROM)
			2.4.3.5 FLASH Memory
			2.4.3.6 Static Random Access Memory (SRAM)
			2.4.3.7 Dynamic Random Access Memory (DRAM)
			2.4.3.8 Ferroelectric Random Access Memory (FRAM)
				Concept Check
3: Computer Systems
	3.1 Computer Overview
		Concept Check
	3.2 Computer Hardware
		3.2.1 Program Memory
		3.2.2 Data Memory
		3.2.3 Central Processing Unit
			3.2.3.1 Control Unit
			3.2.3.2 Registers
			3.2.3.3 Arithmetic Logic Unit (ALU)
		3.2.4 Input/Output Ports
		3.2.5 Bus System
			Concept Check
	3.3 Computer Software
		3.3.1 Classes of Instructions
			3.3.1.1 Data Movement Instructions
			3.3.1.2 Data Manipulation Instructions
			3.3.1.3 Program Flow Instructions
		3.3.2 Op-codes and Operands
			Concept Check
		3.3.3 Program Development Flow
4: The MSP430
	4.1 MSP430 Hardware Overview
		4.1.1 Word Versus Byte Memory Access
		4.1.2 Program Memory
		4.1.3 Data Memory
		4.1.4 Central Processing Unit
			4.1.4.1 Registers
			4.1.4.2 ALU
		4.1.5 Input/Output Ports and Peripherals
			4.1.5.1 Digital I/O
			4.1.5.2 Serial I/O
			4.1.5.3 Timers
			4.1.5.4 Analog-to-Digital Converter
			4.1.5.5 Digital-to-Analog Converters
			4.1.5.6 Clock System
			4.1.5.7 Power Management Module
		4.1.6 Bus System
		4.1.7 MSP430 Part Numbering
			Concept Check
	4.2 MSP430 Software Overview
		4.2.1 The MSP430 Instruction Set
		4.2.2 Word (.W) Versus Byte (.B) Operations
		4.2.3 The TI Code Composer Studio Development Environment
			Concept Check
	4.3 MSP430FR2355 LaunchPad Development Kit
		Concept Check
5: Getting Started Programming the MSP430 in Assembly
	5.1 The Anatomy of an Assembly Program File
		5.1.1 Instruction Statements
		5.1.2 Assembler Directives
		5.1.3 Miscellaneous Syntax Notes
			5.1.3.1 Identifiers
			5.1.3.2 Sections
			5.1.3.3 Case Sensitivity
				Concept Check
	5.2 Your First Program: Blinking LED
		Concept Check
	5.3 Using the CCS Debugger
		5.3.1 Resume, Terminate, and Suspend
		5.3.2 Breakpoints
		5.3.3 Viewing Register Contents
		5.3.4 Viewing the Contents of Memory
		5.3.5 Stepping Your Program
			Concept Check
6: Data Movement Instructions
	6.1 The MOV Instruction with Register Mode (Rn) Addressing
		Concept Check
	6.2 The MOV Instruction with Immediate Mode (#N) Addressing
		Concept Check
	6.3 The MOV Instruction with Absolute Mode (&ADDR) Addressing
		Concept Check
	6.4 The MOV Instruction with Symbolic Mode (ADDR) Addressing
		Concept Check
	6.5 The MOV Instruction with Indirect Register Mode (@Rn) Addressing
		Concept Check
	6.6 The MOV Instruction with Indirect Autoincrement Mode (@Rn+) Addressing
		Concept Check
	6.7 The MOV Instruction with Indexed Mode (X(Rn)) Addressing
		Concept Check
7: Data Manipulation Instructions
	7.1 Arithmetic Instructions
		7.1.1 Addition Instructions
		7.1.2 Subtraction Instructions
		7.1.3 Increments and Decrements
			Concept Check
	7.2 Logic Instructions
		Concept Check
	7.3 Bit Set and Bit Clear Instructions
		Concept Check
	7.4 Test Instructions
		Concept Check
	7.5 Rotate Operations
		Concept Check
8: Program Flow Instructions
	8.1 Unconditional Jumps and Branches
		Concept Check
	8.2 Conditional Jumps
		8.2.1 Carry-Based Jumps
		8.2.2 Zero-Based Jumps
		8.2.3 Negative-Based Jumps
		8.2.4 Overflow-Based Jumps
			Concept Check
	8.3 Implementing Common Programming Constructs in Assembly
		8.3.1 Implementing While() Loop Functionality
		8.3.2 Implementing For() Loop Functionality
		8.3.3 Implementing If/Else Functionality
		8.3.4 Implementing Switch/Case Functionality in Assembly
			Concept Check
	8.4 Flow Charts
		Concept Check
9: Digital I/O
	9.1 The MSP430 Digital I/O System
		9.1.1 Port Direction Registers (PxDIR)
		9.1.2 Port Input Registers (PxIN)
		9.1.3 Port Output Registers (PxOUT)
		9.1.4 Port Pull-up or Pull-down Resistor Enable Registers (PxREN)
		9.1.5 Port Function Select Registers (PxSEL1 and PxSEL0)
		9.1.6 Digital I/O Enabling After Reset
		9.1.7 Using Literal Definitions from the MSP430.H Header File
			Concept Check
	9.2 Digital Output Programming
		Concept Check
	9.3 Digital Input Programming
		Concept Check
10: The Stack and Subroutines
	10.1 The Stack
		Concept Check
	10.2 Subroutines
		Concept Check
11: Introduction to Interrupts
	11.1 The Concept of an Interrupt
		11.1.1 Interrupt Flags (IFG)
		11.1.2 Interrupt Priority and Enabling
		11.1.3 Interrupt Vectors
		11.1.4 Operation of the Stack during an IRQ
		11.1.5 Interrupt Service Routines (ISR)
		11.1.6 Nested Interrupts
		11.1.7 Interrupt Servicing Summary
		11.1.8 MSP430FR2355 Interrupts
			Concept Check
	11.2 MSP430FR2355 Port Interrupts
		Concept Check
12: Introduction to Timers
	12.1 Timer Overview
		Concept Check
	12.2 Timer Overflows on the MSP430FR2355
		Concept Check
	12.3 Timer Compares on the MSP430FR2355
		Concept Check
	12.4 Creating Pulse Width Modulated Signals Using Timer Compares
		Concept Check
	12.5 Timer Captures on the MSP430FR2355
		Concept Check
13: Switching to the C Language
	13.1 Basics of C Programming on the MSP430
		13.1.1 While() Loops in C
		13.1.2 For() Loops in C
		13.1.3 If/Else Statements in C
		13.1.4 Switch/Case Statements in C
		13.1.5 Arithmetic Operators in C
		13.1.6 Bitwise Logic Operators in C
			Concept Check
	13.2 Digital I/O in C
		Concept Check
	13.3 Interrupts in C
		Concept Check
	13.4 Timers in C
		Concept Check
14: Serial Communication in C
	14.1 Universal Asynchronous Receiver/Transmitter (UART)
		14.1.1 The UART Standard
		14.1.2 UART Transmit on the MSP430FR2355
		14.1.3 UART Receive on the MSP430FR2355
			Concept Check
	14.2 Serial Peripheral Interface (SPI)
		14.2.1 The SPI Protocol
		14.2.2 SPI Master Operation on the MSP430FR2355
			14.2.2.1 Transmitting Data as the SPI Master
			14.2.2.2 Receiving Data as the SPI Master
		14.2.3 SPI Slave Operation on the MSP430FR2355
			14.2.3.1 Transmitting Data as a SPI Slave
			14.2.3.2 Receiving Data as a SPI Slave
				Concept Check
	14.3 Inter-integrated Circuit (I2C) Bus
		14.3.1 The I2C Protocol
		14.3.2 I2C Master Operation on the MSP430FR2355
			14.3.2.1 Writing Data as an I2C Master
			14.3.2.2 Reading Data as an I2C Master
		14.3.3 I2C Slave Operation on the MSP430FR2355
			Concept Check
15: Analog-to-Digital Converters
	15.1 Analog-to-Digital Converters
		Concept Check
	15.2 ADC Operation on the MSP430FR2355
		Concept Check
16: The Clock System
	16.1 Overview of the MSP430FR2355 Clock System
		16.1.1 Internal Very Low-Power Low-Frequency Oscillator (VLO)
		16.1.2 Internal Trimmed Low-Frequency Reference Oscillator (REFO)
		16.1.3 External XT1 Oscillator (XT1)
		16.1.4 Internal Digitally Controlled Oscillator (DCO)
		16.1.5 Internal High-Frequency Oscillator (MODCLK)
		16.1.6 Master Clock (MCLK)
		16.1.7 Subsystem Master Clock (SMCLK)
		16.1.8 Auxiliary Clock (ACLK)
		16.1.9 Default Settings on Power-Up
		16.1.10 CS Configuration Registers
			Concept Check
	16.2 Configuring the CS on the MSP430FR2355
		Concept Check
17: Low Power Modes
	17.1 Overview of the MSP430FR2355´s Low Power Modes
		17.1.1 Active Mode (AM)
		17.1.2 Low Power Mode 0 (LPM0): CPU OFF
		17.1.3 Low Power Mode 3 (LPM3): Standby
		17.1.4 Low Power Mode 4 (LPM4): Off
		17.1.5 Low Power Mode 3.5 (LPM3.5): RTC Only
		17.1.6 Low Power Mode 4.5 (LPM4.5): Shutdown
		17.1.7 Example of Putting the MSP430FR2355 into Low Power Mode
			Concept Check
Appendix A: Concept Check Solutions
References
Index