Embedded Computer Systems: Architectures, Modeling, and Simulation. 23rd International Conference, SAMOS 2023 Samos, Greece, July 2–6, 2023 Proceedings

Preface
Organization
Contents
Emerging Technologies
Efficient Handover Mode Synchronization for NR-REDCAP on a Vector DSP
	1 Introduction
	2 UE Activity Profile During Cell Handover in NR REDCAP
	3 Problem Statement
	4 Previous Work
	5 Implementation
		5.1 Processor Architecture
		5.2 Implementation of Orange Column I
		5.3 Optimizations
	6 Results
	7 Conclusion
	References
Fault Detection Mechanisms for COTS FPGA Systems Used in Low Earth Orbit
	1 Introduction
	2 Error Detection Implementation
		2.1 Switch Firmware Redundancy
		2.2 Configuration Integrity Checking
		2.3 Fault Detection Reaction
		2.4 Implementation Summary
	3 Evaluation
		3.1 Resources
		3.2 Fault Injection
	4 Conclusion
	References
NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems
	1 Introduction
	2 Background and Motivation
	3 NTHPC: The Key Concept
		3.1 NTC Sparing
		3.2 Thermal Management: TEI vs. Core Sparing
		3.3 Expected Lifetime Chip Performance (LCP)
	4 Evaluation
	5 Conclusion and Future Work
	References
Power Efficient Technologies
Closing the Capacity Gap: A Transforming Technique for ReRAM-Friendly NNs
	1 Introduction
	2 Background: ReRAM for In-Memory NN Computing
	3 Related Work
	4 Transforming NNs to Reduce the Capacity Gap
		4.1 Algorithm for NN Model Reduction
	5 A ReRAM Architecture for NN Processing
		5.1 Data Flow and Pipeline
		5.2 Local Buffers
		5.3 MVM Unit
		5.4 Enhancement for NN Pruning
	6 Evaluation Methodology
	7 Results
		7.1 Synthesis Results
		7.2 Inference Accuracy and Model Size Reduction
		7.3 Time and Energy Analysis
	8 Conclusion and Future Work
	References
Myrmec: FPGA-Accelerated SmartNIC for Cost and Power Efficient IoT Sensor Networks
	1 Introduction
	2 Background and Related Works
	3 SmartNIC Architecture for Embedded Systems
		3.1 Myrmec Accelerator Architecture
		3.2 Software Interface
	4 Evaluation
		4.1 Application Details
		4.2 Performance Evaluation
		4.3 Power-Efficiency Evaluation
	5 Conclusion and Discussion
	References
Exploring Multi-core Systems with Lifetime Reliability and Power Consumption Trade-offs
	1 Introduction
	2 Related Work
	3 Methodology
		3.1 Simulator
		3.2 Genetic Algorithm
		3.3 Speeding up the GA
	4 Experiments
		4.1 Setup
		4.2 Results
	5 Conclusion
	References
Hardware Accelerators
Characterization of a Coherent Hardware Accelerator Framework for SoCs
	1 Introduction
	2 Background and Motivation
	3 ACAI: A Cache Coherent Framework for Accelerators
		3.1 Overview
		3.2 ACAI Architecture
		3.3 ACAI Software
		3.4 Accelerator Integration with ACAI
		3.5 Usage Overview
		3.6 Limitations
	4 Methodology
		4.1 Evaluation Platform
		4.2 Evaluated Benchmarks
		4.3 Performed Experiments
	5 Evaluation
		5.1 Area Analysis
		5.2 Analysis
	6 Discussion/Future Work
	7 Related Work
	8 Conclusions
	References
DAEBI: A Tool for Data Flow and Architecture Explorations of Binary Neural Network Accelerators
	1 Introduction
	2 System Model
		2.1 Binarized Neural Networks (BNNs)
		2.2 BNN Accelerators
		2.3 Data Flow in BNN Accelerators: OS and WS
	3 Our Tool DAEBI
		3.1 High-Level Overview of DAEBI
		3.2 Implementation of DAEBI and the Hardware Designs
	4 Decision Model for Using OS or WS
	5 Evaluation
		5.1 Experiment Setup
		5.2 Results of Experiments for Classical CMOS Technology
		5.3 Insights for Beyond-CMOS Technology
	6 Conclusion
	References
An Intelligent Image Processing System for Enhancing Blood Vessel Segmentation on Low-Power SoC
	1 Introduction
	2 Blood Vessel Segmentation
		2.1 Vessel Enhancement Approaches
		2.2 Machine Learning Approaches
	3 AI Algorithm and System Model
	4 Experiments
		4.1 GBDT Training
		4.2 MLP Training
		4.3 CNN Training
		4.4 Hardware Implementation
	5 Evaluation
		5.1 Performance Metrics
		5.2 Window Size and ML Models
		5.3 GBDT Compression
		5.4 MLP Compression
		5.5 CNN Compression
	6 Results
		6.1 Benchmarks
		6.2 FPGA Implementation
	7 Conclusions
	References
Quantum and Optical Computing
Micro-architecture and Control Electronics Simulation of Modular Color Center-Based Quantum Computers
	1 Introduction
	2 Related Work
	3 QISA and Micro-ISA
		3.1 Global Controller
		3.2 Local Controller
	4 Simulator Implementation
		4.1 The NetSquid Simulation Framework
		4.2 Global and Local Controller
		4.3 Electronics
	5 Implementation of a Distributed Quantum Protocol
	6 Results
		6.1 Initialize
		6.2 Magnetic Biasing
		6.3 Rabi Oscillation Check
		6.4 DetectCarbon
		6.5 ChargeResonanceCheck
		6.6 Quantum Algorithm
	7 Conclusion
	References
From Algorithm to Implementation: Enabling High-Throughput CNN-Based Equalization on FPGA for Optical Communications
	1 Introduction
	2 Experimental Setup
	3 Design Space Exploration
		3.1 CNN Topology Template
		3.2 Design Space Exploration Framework
		3.3 Quantization
		3.4 Results of Design Space Exploration
	4 Hardware Architecture
		4.1 Stream Partitioning
	5 Sequence Length Optimization
		5.1 Timing Model
		5.2 Optimization Framework
	6 Results
		6.1 Timing Model Validation
		6.2 Implementation Results
		6.3 Platform Comparison
	7 Conclusion
	References
Power Performance Modeling and Simulation
parti-gem5: gem5\'s Timing Mode Parallelised
	1 Introduction
	2 Related Work
	3 Background
		3.1 Discrete Event Simulation in gem5
		3.2 CPU Models in gem5
		3.3 Communication Protocols in gem5
		3.4 The Ruby Cache and Interconnect Subsystem
	4 Parallelising gem5 Timing Models
		4.1 System Partitioning and Main Parallelisation Challenges
		4.2 Thread-Safe Ruby Message Passing
		4.3 Thread-Safe Concurrent Non-coherent Traffic
	5 Experimental Evaluation
		5.1 Setup
		5.2 Results
	6 Conclusion and Outlook
	References
Reliable Basic Block Energy Accounting
	1 Introduction
	2 Related Work
		2.1 Energy Profiling
		2.2 Energy Modeling
		2.3 Basic Block-Level Datasets Aimed for Modeling
	3 Background
		3.1 Basic Blocks
		3.2 RAPL
		3.3 PT
		3.4 Clang-Enabled LLVM Passes
	4 Method
		4.1 Obstacles and Workarounds
	5 Evaluation
		5.1 Experimental Setup
		5.2 Results and Discussion
	6 Conclusions
	References
RattlesnakeJake: A Fast and Accurate Pre-alignment Filter Suitable for Computation-in-Memory
	1 Introduction
	2 Background
		2.1 Sequence Alignment
		2.2 Pre-alignment Filtering
		2.3 Computation-In-Memory (CIM) and Memristors
	3 Proposal and Architecture
		3.1 RattlesnakeJake\'s Algorithm
		3.2 RattlesnakeJake\'s Architecture
		3.3 RattlesnakeJake Algorithm to Hardware Mapping
	4 Evaluations
		4.1 Evaluation Methodology
		4.2 Accuracy Analysis
		4.3 Throughput and Execution Time
	5 Conclusion
	References
Open Hardware RISC-V Technologies
PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations
	1 Introduction
	2 Related Work
	3 Open-Source PATARA Framework
		3.1 REVERSI Approach
		3.2 Open-Source PATARA Framework
	4 Extensions of the PATARA Framework for RISC-V
		4.1 The RISC-V RV32IM ISA
		4.2 RISC-V Extensions Implemented in PATARA Framework
	5 Evaluation Results
	6 Conclusions
	References
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster
	1 Introduction
	2 Related Work
	3 Barriers Implementation
	4 Benchmarking Strategy
		4.1 Benchmarking with Random Delay
		4.2 Benchmarking of Kernels
		4.3 Benchmarking of a 5G-Processing Application
	5 Results
	6 Conclusions
	References
High Performance Instruction Fetch Structure within a RISC-V Processor for Use in Harsh Environments
	1 Introduction
	2 Related Work
	3 General Architecture
	4 Prefetch Lanes
	5 Caching Structure
		5.1 Monolithic Cache
		5.2 Cache Splitting
		5.3 LSB Splitting
		5.4 L0 Register Cache
	6 Evaluation
	7 Conclusion
	References
Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-Based Approach to Simulation and Modeling
	1 Introduction
	2 Background and Related Work
	3 Simulation Platform
		3.1 MPSoC Architecture
		3.2 Network Adapter and API
		3.3 Tool Flow and Application View
	4 Evaluation
	5 Conclusion
	References
Innovative Architectures and Tools for Security
DD-MPU: Dynamic and Distributed Memory Protection Unit for Embedded System-on-Chips
	1 Introduction
	2 Related Work
	3 Architecture
		3.1 Detection Logic
		3.2 Protection Unit
		3.3 Customization for IPs
	4 Case Study
	5 Evaluation
	6 Conclusion
	References
Trust-Based Adaptive Routing for NoCs
	1 Introduction
	2 Related Work
	3 Concept
		3.1 System Model and Assumptions
		3.2 Overview of the Adaptive Routing Algorithm
		3.3 Detection of Modifications and Deletions by Means of Reports
		3.4 Computation of Trust Values
	4 Evaluation
		4.1 Simulation Settings
		4.2 Results
	5 Summary and Outlook
	References
Run-Time Detection of Malicious Behavior Based on Exploit Decomposition Using Deep Learning: A Feasibility Study on SysJoker
	1 Introduction
		1.1 Contribution
	2 Malware Decomposition and Attack Vector Data Collection
		2.1 Attack Model
		2.2 Analyzing Malware Components: SysJoker Use Case
		2.3 Proposed Malicious Behavior Detection Methodology
		2.4 Proposed Dataset Collection
	3 Proposed Deep Learning Approach
		3.1 Problem Formulation and Preprocessing
		3.2 Fully Connected Network Approach
		3.3 Convolutional Neural Network Approach
		3.4 Long Short-Term Memory Neural Network Approach
	4 Results and Analysis
	5 Conclusions and Future Work
	References
A Survey of Software Implementations for the Number Theoretic Transform
	1 Introduction
	2 Preliminaries
		2.1 Lattice-Based Cryptography
		2.2 The Number Theoretic Transform
	3 Categorization Method
	4 Software Implementation Summary
	5 Conclusion
	References
EU Project with Focus on Solutions for Aerospace and Networking
METASAT: Modular Model-Based Design and Testing for Applications in Satellites
	1 Introduction
	2 Project Objectives
	3 Project Innovations
		3.1 Open Hardware, High-Performance Platforms
		3.2 Virtualisation Environment
		3.3 Model-Based Engineering (MBE)
		3.4 Artificial Intelligence Based Design and Testing
		3.5 On-Board Artificial Intelligence for FDIR
	4 Methodology
		4.1 METASAT Digital Twin
		4.2 METASAT Hardware Platform
		4.3 METASAT Use Cases
	5 Conclusions
	References
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project
	1 Introduction
		1.1 The ISOLDE Project
		1.2 Objective of the Paper and Its Organization
	2 Requirements of Modern Space Applications
	3 A RISC-V Processor Family for Onboard AI
	4 Technology Bricks
		4.1 Hardware Accelerators
		4.2 Energy Efficiency, Real-Time, and Power Monitoring
		4.3 Security
		4.4 AI Optimization Toolchain
	5 Concluding Remarks
	References
Towards Privacy-First Security Enablers for 6G Networks: The PRIVATEER Approach
	1 Introduction
	2 PRIVATEER\'s Goals and Addressed Challenges
	3 PRIVATEER\'s Architecture
		3.1 High-Level Overview
		3.2 Decentralised Robust Security Analytics
		3.3 Privacy-Aware Slicing and Orchestration
		3.4 Distributed Attestation
	4 PRIVATEER\'s Use-Cases
	5 Conclusion
	References
EU Project with Focus on HPC
RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters
	1 Introduction
		1.1 The Italian National Center for High Performance Computing
		1.2 Organization of the Paper
	2 Power Evaluation and Management Platforms
		2.1 Power Monitoring
		2.2 Memory Reliability
		2.3 Thermal Management
	3 Reliability Evaluation and Management Platforms
		3.1 Evaluation at the Technology Level
		3.2 Evaluation at Architecture and System Levels
		3.3 System-Level Fault Tolerance for Real-Time Applications
	4 Performance Monitoring and Management
		4.1 Performance and Power Monitoring at the Distributed Level
		4.2 Performance Monitoring of Parallel Applications
		4.3 Estimation of the Probabilistic-WCET
		4.4 Performance Comparison of RISC-V ML Software
	5 Experimental Testbed for Two-Phase Cooling
	6 Concluding Remarks
	References
Enabling an Isolated and Energy-Aware Deployment of Computationally Intensive Kernels on Multi-tenant Environments
	1 Introduction
	2 Overview of the SERRANO Project
		2.1 Challenge for Workload Isolation and Execution Trust on Untrusted Physical Tenders
	3 Background
		3.1 Hardware-Aware Approximation
		3.2 Virtualization Technology
	4 Proposed Framework
		4.1 Hardware-Driven Optimization
		4.2 Isolated Execution
	5 Experimental Results
	6 Conclusion
	References
Quantum Computing Research Lines in the Italian Center for Supercomputing
	1 Introduction
	2 Quantum Computing Applications and Spoke 10 Activities
		2.1 Quantum Computing Applications
		2.2 Spoke 10 Research Topics
	3 A Case Study: Cryptanalytic Algorithms for Post-Quantum Ciphers
	4 Concluding Remarks
	References
Memory-Centric Computing: From Application to Circuits
Devices and Architectures for Efficient Computing In-Memory (CIM) Design
	1 Introduction
	2 Background
		2.1 CIM Basics
		2.2 CIM Benefits
		2.3 VCM Devices and Circuits for CIM
	3 CIM Architectures
		3.1 CIM Architecture Units
		3.2 Potential CIM Applications
	4 Circuits and Devices for CIM
		4.1 Vector-Matrix-Multiplication Accelerators
	5 CIM Challenges
		5.1 Design Challenges
		5.2 Non-ideality Challenges
	6 Conclusion and Future Direction
	References
Poster Session
A Case for Genome Analysis Where Genomes Reside
	1 Introduction and Motivation
	2 Background
	3 Potential Solution and its Research Trusts
	4 Conclusion
	References
ELAION: ML-Based System for Olive Classification with Edge Devices
	1 Introduction and Motivation
	2 System Overview
	3 Prototype Implementation
	4 Conclusions and Future Work
	References
Energy-Efficient BLAS L1 Routines for FPGA-Supported HPC Applications
	1 Introduction and Motivation
	2 Design Approach
	3 Experimental Results
	4 Conclusions and Future Work
	References
Mixed Precision in Heterogeneous Parallel Computing Platforms via Delayed Code Analysis
	1 Introduction
	2 Methodology for GPGPU Precision Tuning
		2.1 Comparison with the State-of-the-Art
	3 Experimental Evaluation
		3.1 Analysis of the Results
	4 Conclusion
	References
On-Chip Memory Access Reduction for Energy-Efficient Dilated Convolution Processing
	1 Introduction
	2 Background
	3 Related Work
	4 Feature Reuse for Dilated Convolution
		4.1 Decomposition of Input Feature Map
		4.2 Extension to Dilated Convolution and Implementation
	5 Results and Evaluation
		5.1 Reduction of Memory Accesses
		5.2 Implementation Costs and Energy Savings
	6 Conclusion
	References
TrueFloat: A Templatized Arithmetic Library for HLS Floating-Point Operators
	1 Introduction
	2 State of the Art
	3 Proposed Approach
	4 Implementation
		4.1 FPBlender Step
		4.2 TrueFloat Arithmetic Library
		4.3 HLS Transformations
		4.4 Example
	5 Experimental Results
	6 Conclusions
	References
VULDAT: Automated Vulnerability Detection from Cyberattack Text
	1 Introduction
	2 Background
		2.1 Cyber Threat Intelligence (CTI)
		2.2 Vulnerability
		2.3 NLP-Based Methods
	3 Overview of VULDAT
	4 VULDAT Methodology
	5 Conclusion
	References
Author Index