Dual Mode Logic: A New Paradigm for Digital IC Design

Preface
Contents
Acronyms
1 Introduction
	1.1 Energy-Efficient and High-Performance Digital DesignLimitations
	1.2 Introduction to the Design of Digital Logic Families
		1.2.1 Complementary Metal Oxide Semiconductor (CMOS)
		1.2.2 Dynamic Logic
			1.2.2.1 The Cascading Challenge and Dynamic Logic Topologies
			1.2.2.2 A Footer Implementation
			1.2.2.3  Low-Voltage Dynamic Logic
		1.2.3 Other Design Styles in Standard CMOS Technology
			1.2.3.1 Pass Transistor Logic (PTL)
			1.2.3.2 Gate Diffusion Input (GDI)
			1.2.3.3 Source-Coupled Logic (SCL) or Current Mode Logic (CML)
	1.3 Energy–Delay (E–D) Tradeoff Paradigms
	1.4 Book Outline
	References
2 Introduction to Dual Mode Logic (DML)
	2.1 DML Concept and Transistor-Level Architecture
	2.2 DML Advantages
		2.2.1 Robust Operation, Inherent Keeper, and HighPerformance
	2.3 DML: The Best of Both Worlds
	References
3 Optimization of DML Gates
	3.1 Introduction
	3.2 Overview: Standard Logical Effort (LE) Model for a Simple CMOS Inverter Chain
	3.3 Logical Effort (LE) Model for a Simple DML Inverter Chain
		3.3.1 Basic Assumptions
		3.3.2 Defining the Optimization Target for a Simple Inverter Chain
		3.3.3 The Complete Un-approximated Method (CS)for DML Sizing Factors of an Inverter Chain
		3.3.4 The Complete Approximated Method (CA) for DML Sizing Factors of an Inverter Chain
		3.3.5 The Semi-approximated Method (SA) for DML Sizing Factors of an Inverter Chain
	3.4 Generalizing the DML-LE Method for Complex Gates and Branches
		3.4.1 Exploring a General DML Gate Delay Structure
		3.4.2 Delay Optimization Under the Complete Approximated (CA) Model for Complex Gates
	3.5 Comparing the DML-LE Methods
		3.5.1 Delay Error for a Given N
		3.5.2 Nopt Comparison
		3.5.3 Delay Error for a Variable N
	3.6 Example of a DML-LE Evaluation: a 40nm Process
	3.7 Conclusion
	References
4 Low-Voltage DML
	4.1 Introduction
	4.2 DML Under Low-Voltage Operation
	4.3 DML Modeling and Sizing Using the Transregional Model
		4.3.1 Modeling Ion Using the Transregional Model
		4.3.2 Low-Voltage DML Sizing Methodology
		4.3.3 Logical Effort Parameters for Low-Voltage Operation
	4.4 DML Benchmark Measurements
		4.4.1 DML Robustness and Design Metrics Under LowVoltage
		4.4.2 Energy and Delay Analysis
	4.5 Conclusion
	References
5 DML Energy-Delay Tradeoffs and Optimization
	5.1 Introduction: Static DML as a Semi-Energy-Optimal CMOS
	5.2 Critical-Path-DML Approaches to Energy Efficiency and High Performance
	5.3 Solution for Critical Path Timing Violations and Energy Consumption Reduction
	5.4 Modular Benchmark Example: Carry Save Adder Design
		5.4.1 The CMOS csa Design
		5.4.2 DML Critical Path Design
	5.5 Energy-Delay Plane as a Function of VDD and n
		5.5.1 The E-D Plane as f(VDD)
		5.5.2 The E-D Plane as f(N)
		5.5.3 Stimuli Input Vector Complexity
	5.6 Conclusion
	References
6 DML Control
	6.1 Coarse-Grain DML Mode Selection Controller
		6.1.1 Dual-Mode Addition (DMADD) Approach Overview
		6.1.2 Dual-Mode2 (DM2) System Architecture and Transistor Sizing
			6.1.2.1 DM2 Architecture
			6.1.2.2 DM2 Transistor Sizing
		6.1.3 Computing Energy Savings
		6.1.4 Benchmark Results and Analysis
			6.1.4.1 Transistor Sizing and Setting the Group Size
			6.1.4.2 Energy Saving Measurements and Bounds
			6.1.4.3 Comparison of DM2 to Brent–Kung and Simple Ripple Carry Adders
			6.1.4.4 Mode Decision Overhead
			6.1.4.5 Design Accuracy Analysis
			6.1.4.6 Reliability
			6.1.4.7 Area Utilization
		6.1.5 Coarse-Grain Control Conclusions
	6.2 Fine-Grain DML Mode Selection Controller
		6.2.1 Design Example: Carry Look-Ahead Adder
			6.2.1.1 Decision Logic
			6.2.1.2 CLA Architecture
		6.2.2 Fine-Grain Controller Simulation Results
		6.2.3 Fine-Grain Control Conclusions
	References
7 Towards a DML Library Characterization and Design with Standard Flow
	7.1 Introduction
	7.2 Characterization and Standard Design Flow Challenges
		7.2.1 Standard Design Flow: Overview and DML Integration Challenges
		7.2.2 Dynamic Operation Mode Design Challenges
			7.2.2.1 Non-unate Boolean Functions
			7.2.2.2 Dynamic Operation Characterization Challenges
	7.3 A Step Forward with DML Standard Design Flow
		7.3.1 Pseudo-static Library and Multi-library Representation
		7.3.2 Pseudo-static Synthesis and Library Mapping
			7.3.2.1 Monotonic (Unate) Network Mapping
			7.3.2.2 Non-unate Network Mapping
			7.3.2.3 Post-Synthesis Netlist Adaptation
			7.3.2.4 Static Timing Analysis (STA)
	7.4 Characterization Process
		7.4.1 Pseudo-static Library
			7.4.1.1 Design Metric Characteristics
			7.4.1.2 Data-to-Data Timing Constraints
		7.4.2 Dynamic Library
			7.4.2.1 Design Metric Characteristics
			7.4.2.2 Timing Constraints
		7.4.3 Static Library
	7.5 Benchmarks and Results
		7.5.1 Characterization
			7.5.1.1 Performance
			7.5.1.2 Area and Leakage
			7.5.1.3 Equivalent Input Capacitance
		7.5.2 Design Flow
	7.6 A Step Towards a DML Standard Flow: Conclusions
	References
8 Towards a DML Optimized Synthesis
	8.1 DML-Optimized Synthesis Challenges
	8.2 DML Synthesis Approach and Constraints
		8.2.1 Constraints
			8.2.1.1 Correct Precharge (CPC)
			8.2.1.2 Footed Gates (FG)
			8.2.1.3 Single Transition Requirement (STR)
		8.2.2 The Approach
	8.3 Implementation Results
		8.3.1 Simulation Methodology
		8.3.2 Simulation Results
	8.4 Automated DML Synthesis: Conclusion
	References
9 Dual Mode Logic in FD-SOI Technology
	9.1 UTBB FD-SOI Technology
	9.2 DML Design Optimization in UTBB FD-SOI Technology
		9.2.1 Design Optimization
		9.2.2 Performance and Robustness Analysis
	9.3 Design: Dynamically Adaptable Multiply-Accumulate Circuit in 28nm FD-SOI
		9.3.1 DML Column Bypassing Partial Product ReductionTree
		9.3.2 Adaptive Final DML Carry-Skip Adder
		9.3.3 Measurement Results
			9.3.3.1 Energy Consumption and Performance
			9.3.3.2 Robustness and Process/Voltage/Temperature Variations
			9.3.3.3 Comparison to the State of the Art
	9.4 Conclusion
	References
10 Conclusion
A SA Method for the Sizing Factors of DML Inverter Chain
Index