Digital Systems Design Using VHDL 3rd Edition

Cover
Title Page
©
Contents
Preface
About the Authers
1 Review of Logic Design Fundamentals
	1.1 Combinational Logic
	1.2 Boolean Algebra and Algebraic Simplification
	1.3 Karnaugh Maps
		1.3.1 Simplification Using Map-Entered Variables
	1.4 Designing With NAND and NOR Gates
	1.5 Hazards in Combinational Circuits
	1.6 Flip-Flops and Latches
	1.7 Mealy Sequential Circuit Design
		1.7.1 Mealy Machine Design Example 1: Sequence Detector
		1.7.2 Mealy Machine Design Example 2: BCD to Excess-3Code Converter
	1.8 Moore Sequential Circuit Design
		1.8.1 Moore Machine Design Example 1: Sequence Detector
		1.8.2 Moore Machine Design Example 2: NRZ to Manchester Code Converter
	1.9 Equivalent States and Reduction of State Tables
	1.10 Sequential Circuit Timing
		1.10.1 Propagation Delays: Setup and Hold Times
	1.11 Tristate Logic and Busses
	Problems
2 Introduction to VHD
	2.1 Computer-Aided Design
	2.2 Hardware Description Languages
		2.2.1 Learning a Language
	2.3 VHDL Description of Combinational Circuits
	2.4 VHDL Modules
		2.4.1 Four-Bit Full Adder
		2.4.2 Use of “Buffer” Mode
	2.5 Sequential Statements and VHDL Processes
	2.6 Modeling Flip-Flops Using VHDL Processes
	2.7 Processes Using Wait Statements
	2.8 Two Types of VHDL Delays: Transport and Inertial Delays
	2.9 Compilation, Simulation, and Synthesis of VHDL Code
		2.9.1 Simulation with Multiple Processes
	2.10 VHDL Data Types and Operators
		2.10.1 Data Types
		2.10.2 VHDL Operators
	2.11 Simple Synthesis Examples
	2.12 VHDL Models for Multiplexers
		2.12.1 Using Concurrent Statements
		2.12.2 Using Processes
	2.13 VHDL Libraries
	2.14 Modeling Registers and Counters Using VHDL Processes
	2.15 Behavioral and Structural VHDL
		2.15.1 Modeling a Sequential Machine
	2.16 Variables, Signals, and Constants
		2.16.1 Constants
	2.17 Arrays
		2.17.1 Matrices
	2.18 Loops in VHDL
	2.19 Assert and Report Statements
	2.20 Tips for Debugging VHDL Code
	Problems
3 Introduction to Programmable Logic Devices
	3.1 Brief Overview of Programmable Logic Devices
	3.2 Simple Programmable Logic Devices
		3.2.1 Read-Only Memories
		3.2.2 Programmable Logic Arrays
		3.2.3 Programmable Array Logic
		3.2.4 Programmable Logic Devices/Generic Array Logic
	3.3 Complex Programmable Logic Devices
		3.3.1 An Example CPLD: The Xilinx CoolRunner
	3.4 Field Programmable Gate Arrays
		3.4.1 Organization of FPGAs
		3.4.2 FPGA Programming Technologies
		3.4.3 Programmable Logic Block Architectures
		3.4.4 Programmable Interconnects
		3.4.5 Programmable I/O Blocks in FPGAs
		3.4.6 Dedicated Specialized Components in FPGAs
		3.4.7 Applications of FPGAs
		3.4.8 Design Flow for FPGAs
	Untitled
	Problems
4 Design Examples
	4.1 BCD to Seven-Segment Display Decoder
	4.2 A BCD Adder
	4.3 32-Bit Adders
		4.3.1 Carry Look-Ahead Adders
		4.3.2 Parallel Prefix Adders
		4.3.3 Discussion
	4.4 Traffic Light Controller
	4.5 State Graphs for Control Circuits
	4.6 Scoreboard and Controller
		4.6.1 Data Path
		4.6.2 Controller
		4.6.3 VHDL Model
	4.7 Synchronization and Debouncing
		4.7.1 Single Pulser
	4.8 Add-and-Shift Multiplier
	4.9 Array Multiplier
		4.9.1 VHDL Coding
	4.10 A Signed Integer/Fraction Multiplier
	4.11 Keypad Scanner
		4.11.1 Scanner
		4.11.2 Debouncer
		4.11.3 Decoder
		4.11.4 Controller
		4.11.5 VHDL Code
		4.11.6 Test Bench for Keypad Scanner
	4.12 Binary Dividers
		4.12.1 Unsigned Divider
		4.12.2 Signed Divider
	Problems
5 SM Charts and Microprogramming
	5.1 State Machine Charts
	5.2 Derivation of SM Charts
		5.2.1 Binary Multiplier
		5.2.2 A Dice Game
	5.3 Realization of SM Charts
		5.3.1 Implementation of Binary Multiplier Controller
	5.4 Implementation of the Dice Game
	5.5 Microprogramming
		5.5.1 Two-Address Microcode
		5.5.2 Single-Qualifier, Single-Address Microcode
		5.5.3 Microprogramming the Dice Controller
	5.6 Linked State Machines
	Problems
6 Designing with Field Programmable Gate
Arrays
	6.1 Implementing Functions in FPGAs
	6.2 Implementing Functions Using Shannon’s Decomposition
	6.3 Carry Chains in FPGAs
	6.4 Cascade Chains in FPGAs
	6.5 Examples of Logic Blocks in Commercial FPGAs
	6.6 Dedicated Memory in FPGAs
		6.6.1 VHDL Models for Inferring Memory in FPGAs
	6.7 Dedicated Multipliers in FPGAs
	6.8 Cost of Programmability
	6.9 FPGAs and One-Hot State Assignment
	6.10 FPGA Capacity: Maximum Gates versus Usable Gates
	6.11 Design Translation (Synthesis)
		6.11.1 Synthesis of a Case Statement
		6.11.2 Synthesis of if Statements
		6.11.3 Synthesis of Arithmetic Components
		6.11.4 Area, Power, and Delay Optimizations
	6.12 Mapping, Placement, and Routing
		6.12.1 Mapping
		6.12.2 Place and Route
	Problems
7 Floating-Point Arithmetic
	7.1 Representation of Floating-Point Numbers
		7.1.1 A Simple Floating-Point Format Using 2’s Complement
		7.1.2 The IEEE 754 Floating-Point Formats
	7.2 Floating-Point Multiplication
	7.3 Floating-Point Addition
	7.4 Other Floating-Point Operations
		7.4.1 Subtraction
		7.4.2 Division
	Problems
8  Additional Topics in VHD
	8.1 VHDL Functions
	8.2 VHDL Procedures
	8.3 VHDL Predefined Function Called NOW
	8.4 Attributes
		8.4.1 Signal Attributes
		8.4.2 Array Attributes
		8.4.3 Use of Attributes
	8.5 Creating Overloaded Operators
	8.6 Multivalued Logic and Signal Resolution
		8.6.1 A 4-Valued Logic System
		8.6.2 Signal Resolution Functions
	8.7 The IEEE 9-Valued Logic System
		8.7.1 Synthesis using IEEE 1164
	8.8 SRAM Model Using IEEE 1164
	8.9 Model for SRAM Read/Write System
	8.10 Generics
	8.11 Named Association
	8.12 Generate Statements
		8.12.1 Conditional Generate
	8.13 Files and TEXTIO
	Problems
9 Design of RISC Microprocessors
	9.1 The RISC Philosophy
	9.2 The MIPS ISA
		9.2.1 Arithmetic Instructions
		9.2.2 Logical Instructions
		9.2.3 Memory Access Instructions
		9.2.4 Control Transfer Instructions
	9.3 MIPS Instruction Encoding
	9.4 Implementation of a MIPS Subset
		9.4.1 Design of the Data Path
		9.4.2 Instruction Execution Flow
	9.5 VHDL Model of the MIPS Subset
		9.5.1 VHDL Model for the Register File
		9.5.2 VHDL Model for Memory
		9.5.3 VHDL Code for the MIPS Processor CPU
		9.5.4 Complete MIPS
		9.5.5 Testing the MIPS Processor Model
		Untitled
	9.6 Design of an ARM Processor
		9.6.1 The ARM ISA
	9.7 ARM Instruction Encoding
		9.7.1 Data Processing Instructions
		9.7.2 Multiply Instructions
		9.7.3 Memory Access Instruction Formats
		9.7.4 Branch instructions
	9.8 Implementation of a Subset of ARM Instructions
		9.8.1 Design of the Data Path
		9.8.2 Instruction Execution Flow
	9.9 VHDL Model of the ARM Subset
		9.9.1 VHDL Model for the Register File
		9.9.2 VHDL Model for Memory
		9.9.3 VHDL Code for the ARM Processor CPU
		9.9.4 Integrated ARM
		9.9.5 Testing the ARM Processor Model
	Problems
10 Verifcation of Digital Systems
	10.1 Importance of Verification
	10.2 Verification Terminology
	10.3 Functional Verification
		10.3.1 Self-Checking Test Benches
		10.3.2 Verification Flow
		10.3.3 Verification Approaches
		10.3.4 Verification Languages
	10.4 Timing Verification
		10.4.1 Sequential Circuit Timing Basics
		10.4.2 Static Timing Analysis
	10.5 Static Timing Analysis for Circuits with No Skew
		10.5.1 Timing Rules for Flip-Flop to Flip-Flop Paths
	10.6 Static Timing Analysis for Circuits with Clock Skew
		10.6.1 Timing Rules for Circuits with Skew
	10.7 Glitches in Sequential Circuits
	10.8 Clock Gating
	10.9 Clock Distribution Circuitry
		10.9.1 Asynchronous Design
	Problems
11 Hardware Testing and Design for  Testability
	11.1 Faults and Fault Models
	11.2 Testing Combinational Logic
	11.3 Testing Sequential Logic
	11.4 Scan Testing
	11.5 Boundary Scan
	11.6 Memory Testing
		11.6.1 Standard Memory Test Patterns
	11.7 Built-In Self-Test
	Problems
Appendices
	Appendix A: VHDL Language Summaary
	Appendix B: IEEE Standard Libraries
	Appendix C: Textio Package
	Appendix D: Projects
References
Index