Digital logic design using Verilog : coding and RTL synthesis

Preface
Acknowledgements
Contents
About the Author
1 Introduction
	1.1 Evolution of Logic Design
	1.2 System and Logic Design Abstractions
		1.2.1 Architecture Design
		1.2.2 Micro-architecture Design
		1.2.3 RTL Design and Synthesis
		1.2.4 Switch Level Design
	1.3 Integrated Circuit Design and Methodologies
		1.3.1 RTL Design
		1.3.2 Functional Verification
		1.3.3 Synthesis
		1.3.4 Physical Design
	1.4 Verilog as Hardware Description Language
	1.5 Verilog Design Description
		1.5.1 Structural Design
		1.5.2 Behavior Design
		1.5.3 Synthesizable Design
	1.6 Few Important Verilog Terminologies
	1.7 Exercises
	1.8 Summary
2 Concept of Concurrency and Verilog Operators
	2.1 Use of Continuous Assignment to Model Design
	2.2 Use of always Procedural Block to Implement Combinational Design
	2.3 Concept of Concurrency
	2.4 Verilog Arithmetic Operators
	2.5 Verilog Logical Operators
	2.6 Verilog Equality and Inequality Operators
	2.7 Verilog Sign Operators
	2.8 Verilog Bitwise Operators
	2.9 Verilog Relational Operators
	2.10 Verilog Concatenation and Replication Operators
	2.11 Verilog Reduction Operators
	2.12 Verilog Shift Operators
	2.13 Exercises
	2.14 Summary
3 Verilog Constructs and Combinational Design-I
	3.1 The Role of Constructs
	3.2 Logic Gates and Synthesizable RTL
		3.2.1 NOT or Invert Logic
		3.2.2 OR Logic
		3.2.3 NOR Logic
		3.2.4 AND Logic
		3.2.5 NAND Logic
		3.2.6 Two Input XOR Logic
		3.2.7 Two Input XNOR Logic
	3.3 Tristate Logic
	3.4 Arithmetic Circuits
		3.4.1 Adder
			3.4.1.1 Half Adder
			3.4.1.2 Full Adder
		3.4.2 Subtractor
			3.4.2.1 Half Subtractor
			3.4.2.2 Full Subtractor
	3.5 Exercises
	3.6 Summary
4 Verilog Constructs and Combinational Design-II
	4.1 Procedural Block always @*
	4.2 Multi-bit Adders and Subtractors
		4.2.1 Four-Bit Full Adder
		4.2.2 4-Bit Full Subtractor
		4.2.3 4-Bit Adder and Subtractor
	4.3 Optimization of Resources
		4.3.1 Optimization Using Only Adders
		4.3.2 Optimization by Tweaking the Logic to Have Better Data and Control Path
	4.4 Procedural Block initial
	4.5 Simulation Concepts: Basic Testbench
	4.6 Comparators and Parity Detectors
		4.6.1 Binary Comparators
		4.6.2 Parity Detector
	4.7 Code Converters
		4.7.1 Binary to Gray Code Converter
		4.7.2 Gray to Binary Code Converter
	4.8 Let Us Think About the Design from Specifications
	4.9 Exercises
	4.10 Summary
5 Multiplexers as Universal Logic
	5.1 Multiplexers
	5.2 Multiplexer as Universal logic
		5.2.1 2:1 MUX
	5.3 The if...else Versus case Construct
	5.4 The 4:1 MUX Using if...else
	5.5 The 4:1 MUX Using case Construct
	5.6 The 4:1 Mux Using 2:1 MUX
	5.7 Let Us Design Combinational Logic Using Multiplexers
	5.8 Optimization Strategies Using RTL Tweaks
	5.9 Exercises
	5.10 Summary
6 Decoders and Encoders
	6.1 Decoders
		6.1.1 1 Line to 2 Decoder Using case construct
		6.1.2 1 Line to 2 Decoder Having Enable Using case
		6.1.3 2 Line to 4 Decoder with Enable Using case
		6.1.4 2 Line to 4 Decoder with Active Low Enable Using case
		6.1.5 2 to 4 Decoder Using Continuous Assignments
		6.1.6 Decoder Using Shift Operator
		6.1.7 Testbench of 2:4 Decoder
		6.1.8 4 Line to 16 Decoder Using 2:4 Decoder
	6.2 Testbench for 4:16 Decoder
	6.3 Encoders
		6.3.1 Priority Encoders
	6.4 Testbench of 4:2 Priority encoder
	6.5 Exercises
	6.6 Summary
7 Event Queue and Design Guidelines
	7.1 Verilog Stratified Event Queue
	7.2 Verilog Blocking Assignments
	7.3 Incomplete Sensitivity List
	7.4 Continuous Versus Procedural Assignments
	7.5 Combinational Loops in Design
	7.6 Unintentional Latches in the Design
	7.7 Use of Blocking Assignments
	7.8 Use of if...else Versus case constructs
	7.9 Nested Multiplexer or Priority Logic
	7.10 Parallel Logic or Decoding Logic
	7.11 Priority Encoding Structure
	7.12 Missing default Condition in case construct
	7.13 Nested if...else with Missing else Condition
	7.14 Logical Equality Versus Case Equality
		7.14.1 Logical Equality and Logical Inequality Operators
		7.14.2 Case Equality and Case Inequality Operators
	7.15 Multiple Driver Assignments
	7.16 Exercises
	7.17 Summary
8 Basics of Sequential Design Using Verilog
	8.1 Sequential Logic
		8.1.1 Positive-Level Sensitive D Latch
		8.1.2 Negative-Level Sensitive D Latch
	8.2 Flip-Flop
		8.2.1 Positive Edge-Triggered D Flip-Flop
		8.2.2 Negative Edge-Triggered D Flip-Flop
		8.2.3 Synchronous and Asynchronous Reset
			8.2.3.1 D Flip-Flop Having Asynchronous Reset
		8.2.4 D Flip-Flop Having Synchronous Reset
		8.2.5 Flip-Flop Having Synchronous Load Enable and Asynchronous Reset
		8.2.6 Flip-Flop with Synchronous Load and Synchronous Reset
	8.3 Exercises
	8.4 Summary
9 Synchronous Counter Design Using Synthesizable Constructs
	9.1 Synchronous Counters
		9.1.1 Three-Bit Up Counter
		9.1.2 Three-Bit Down Counter
		9.1.3 Three-Bit Up–Down Counter
	9.2 Gray Counters
		9.2.1 Gray and Binary Counter
		9.2.2 Ring Counters
		9.2.3 Johnson Counters
	9.3 BCD Up–Down Counter
	9.4 Exercises
	9.5 Summary
10 RTL Design of Registers and Memories
	10.1 Parallel Input and Parallel Output (PIPO) Register
	10.2 Shift Register
	10.3 Right and Left Shift Operation
	10.4 Timing and Performance Evaluation
	10.5 Asynchronous Counter Design
		10.5.1 Ripple Counters
	10.6 RTL Design of Memories
	10.7 Parameterized Read–Write Memory
	10.8 Exercises
	10.9 Summary
11 Sequential Circuit Design Guidelines
	11.1 What Happens If Blocking Assignments Are Used to Code Sequential Logic?
		11.1.1 Blocking Assignments and Multiple always Blocks
		11.1.2 Multiple Blocking Assignments Used in the Single always Block
		11.1.3 Example Blocking Assignment
	11.2 Non-blocking Assignments
		11.2.1 Example Non-blocking Assignments
		11.2.2 Example Non-blocking Assignment
		11.2.3 Example Using Non-blocking Assignments
	11.3 Latch Versus Flip-Flop
		11.3.1 D Flip-Flop
		11.3.2 Latch
	11.4 Use of Synchronous Versus Asynchronous Reset
		11.4.1 D Flip-Flop Having Asynchronous Reset
		11.4.2 Synchronous Reset D Flip-Flop
	11.5 Use of if...else Versus case constructs
	11.6 Internally Generated Clocks
	11.7 Guidelines for Modeling Synchronous Designs
	11.8 Multiple Clocks in the Same module
	11.9 Multi-phase Clocks in the Design
	11.10 Guidelines for Modeling Asynchronous Designs
	11.11 Exercises
	11.12 Summary
12 RTL Design Strategies for Complex Designs
	12.1 ALU Design
		12.1.1 Logic Unit Design
			12.1.1.1 Logic Unit to Infer Parallel Logic
			12.1.1.2 Logic Unit Having Registered Inputs and Outputs
		12.1.2 Arithmetic Unit
		12.1.3 Arithmetic and Logic Unit
	12.2 Functions and Tasks
		12.2.1 Counting Number of 1’s from the Given String
		12.2.2 RTL Design Using function to Count Number of 1’S
	12.3 Synthesis Result of RTL Using function
	12.4 Synthesis Result of RTL Using task
	12.5 Exercises
	12.6 Summary
13 RTL Tweaks and Performance Improvement Techniques
	13.1 Arithmetic Resource Sharing
		13.1.1 RTL Design Using Resource Sharing to Have Area Optimization
	13.2 Gated Clocks and Dynamic Power Reduction
	13.3 Use of Pipelining in Design
		13.3.1 Design Without Pipelining
		13.3.2 Speed Improvement Using Register Balancing or Pipelining
	13.4 Counter Design and Duty Cycle Control
	13.5 MOD-3 Counter RTL Design to Have 50% Duty Cycle
	13.6 Exercise
	13.7 Summary
14 Finite State Machines Using Verilog
	14.1 Moore Versus Mealy Machines
		14.1.1 Level to Pulse Converter
	14.2 FSM Encoding Styles
		14.2.1 Binary Encoding
			14.2.1.1 Two-Bit Binary Counter FSM
		14.2.2 Gray Encoding
			14.2.2.1 Two-Bit Gray Counter FSM
	14.3 One-Hot Encoding
	14.4 Sequence Detectors Using FSMs
		14.4.1 Mealy Sequence Detector Using Two always Procedural Blocks
		14.4.2 Mealy Machine: Sequence Detector to Detect 101 Overlapping Sequence
	14.5 Improving the Design Performance for FSMs
	14.6 Exercises
	14.7 Summary
15 Non-synthesizable Verilog Constructs and Testbenches
	15.1 Intra-delay and Inter-delay Assignments
		15.1.1 Simulation for Blocking Assignments
		15.1.2 Simulation of Non-blocking Assignments
	15.2 The always and initial Procedural Block
		15.2.1 Blocking Assignments with Inter-assignment Delays
		15.2.2 Blocking Assignments with Intra-assignment Delays
		15.2.3 Non-blocking Assignments with Inter-assignment Delays
		15.2.4 Non-blocking Assignments with Intra-assignment Delays
	15.3 Role of Testbenches
	15.4 Multiple Assignments Within the begin–end
	15.5 Multiple Assignments Within the fork–join
	15.6 Display Tasks
	15.7 Exercises
	15.8 Summary
16 FPGA Architecture and Design Flow
	16.1 Introduction to PLD
	16.2 FPGA as Programmable ASIC
		16.2.1 SRAM Based FPGA
		16.2.2 Flash Based FPGA
		16.2.3 Antifuse FPGAS
		16.2.4 Important FPGA Blocks
	16.3 FPGA Design Flow
		16.3.1 Design Entry
		16.3.2 Design Simulation and Synthesis
		16.3.3 Design Implementation
		16.3.4 Device Programming
	16.4 Logic Realization Using FPGA
		16.4.1 Configurable Logic Block
		16.4.2 Input Output Block (IOB)
		16.4.3 Block RAM
		16.4.4 Digital Clock Manager (DCM) Block
		16.4.5 Multiplier Block
	16.5 Exercises
	16.6 Summary
17 FPGA Design and Guidelines
	17.1 Design Guidelines for FPGA Based Designs
		17.1.1 Verilog Coding Guidelines
			17.1.1.1 Blocking Versus Non-blocking Assignments: (Please Refer Chaps. 7 and 11)
			17.1.1.2 Priority Versus Parallel Logic
		17.1.2 FSM Guidelines
	17.2 Combinational Design and Combinational Loops
	17.3 Grouping the Terms
		17.3.1 Assignments
	17.4 Simulation and Synthesis Mismatch
		17.4.1 Post-synthesis Verification
	17.5 Guidelines for Area Optimization
		17.5.1 Resource Sharing
		17.5.2 Logic Duplication
	17.6 Guidelines for Clock
	17.7 Synchronous Versus Asynchronous Designs
	17.8 Guidelines for Use of Reset
	17.9 Guidelines for CDC
	17.10 Guidelines for Low Power Design
	17.11 Guidelines for Use of Vendor-Specific IP Blocks
	17.12 Summary
18 ASIC Design
	18.1 What Is ASIC?
		18.1.1 Full Custom ASIC
		18.1.2 Standard Cell ASIC
		18.1.3 Gate Array ASIC
	18.2 ASIC Design Flow
		18.2.1 Design Specification
		18.2.2 RTL Design and Verification
		18.2.3 ASIC Synthesis
		18.2.4 Physical Design and Implementation:
	18.3 ASIC Design and Synthesis Strategies
	18.4 Summary
19 ASIC Synthesis and SDC Commands
	19.1 ASIC Synthesis Using Design Compiler
	19.2 ASIC Synthesis Guidelines
	19.3 Constraining Design Using Synopsys DC
		19.3.1 Reading the Design
		19.3.2 Checking of the Design
		19.3.3 Clock Definitions
		19.3.4 Skew Definition
		19.3.5 Specifying the Input and Output Delay
		19.3.6 Specify the Minimum (min) and Maximum (Max) Delay
		19.3.7 Design Synthesis
		19.3.8 Command to Save the Design
	19.4 Synthesis and Optimization Techniques
		19.4.1 Resource Allocation
		19.4.2 Common Factors and Sub-expression Use During Optimization
		19.4.3 Moving the Piece of Code
		19.4.4 Constant Folding
		19.4.5 Dead Zone Elimination
		19.4.6 Use of Parentheses
		19.4.7 Partitioning and Structuring the Design
	19.5 Summary
20 Static Timing Analysis
	20.1 Setup Time
	20.2 Hold Time
	20.3 Clock to Q Delay
		20.3.1 Frequency Calculations
	20.4 Skew in Design
	20.5 Timing Paths in Design
		20.5.1 Input-to-Register Path
		20.5.2 Register-to-Output Path
		20.5.3 Register-to-Register Path
		20.5.4 Input-to-Output Path
	20.6 Timing Goals for the Design
	20.7 Min–Max Analysis for ASIC Design
	20.8 Fixing Design Violations
		20.8.1 Tweaks at the Architecture Level
		20.8.2 Tweaks at Micro-architecture Level
		20.8.3 Optimization During Synthesis
	20.9 Fixing Setup Violations in the Design
		20.9.1 Logic Duplication
		20.9.2 Encoding Methods
		20.9.3 Late Arrival Signals
		20.9.4 Register Balancing
	20.10 Hold Violation Fix
	20.11 Timing Exceptions in the Design
		20.11.1 Asynchronous and False Paths
		20.11.2 Multi-cycle Paths
	20.12 Pipelining and Performance Improvement
	20.13 Summary
21 Design Constraints And Optimization
	21.1 Introduction to Design Constraints
	21.2 Compilation Strategy
		21.2.1 Top-Down Compilation
		21.2.2 Bottom-Up Compilation
	21.3 Area Optimization Techniques
		21.3.1 Avoid Use of Combinational Logic as Individual Block
		21.3.2 Avoid Use of Glue Logic Between Two Modules
		21.3.3 Use of Set_max_area Attribute
		21.3.4 Area Report
	21.4 Timing Optimization and Performance Improvement
		21.4.1 Design Compilation Using Map_effort High
		21.4.2 Logical Flattening
		21.4.3 Use of Group_path Command
	21.5 Sub-module Characterizing
	21.6 Register Balancing
	21.7 FSM Optimization
	21.8 Fixing Hold Violations
	21.9 Report Command
		21.9.1 Report_qor
		21.9.2 Report _constraints
			21.9.2.1 Report_contraints_all
	21.10 Constraint Validation
	21.11 Commands Used for the DRC, Power, and Optimization
	21.12 Summary
22 Multiple Clock Domain Design
	22.1 What Is Multiple Clock Domain?
	22.2 What Is Clock Domain Crossing (CDC)
	22.3 Level synchronizers
	22.4 Pulse Synchronizers
	22.5 MUX Synchronizer
	22.6 Challenges in the Design of Synchronizers
	22.7 Data Path Synchronizers
		22.7.1 Handshaking Mechanism
		22.7.2 FIFO Synchronizer
		22.7.3 Gray Encoding
			22.7.3.1 Gray to Binary Converter
			22.7.3.2 Binary to Gray Converter
		22.7.4 Gray Counter
	22.8 Design Guidelines for the Multiple Clock Domain Designs
	22.9 Summary
23 Case Study: FIFO Design
	23.1 FIFO Depth Calculations
		23.1.1 Asynchronous FIFO Depth Calculations
	23.2 FIFO Design Case Study
	23.3 Testbench for FIFO
	23.4 Summary
24 Low Power Design
	24.1 Introduction to Low Power Design
	24.2 Power Dissipation in CMOS NOT Gate
	24.3 Switching and Leakage Power Reduction Techniques
		24.3.1 Clock Gating and Clock Tree Optimizations
		24.3.2 Operand Isolations
		24.3.3 Multiple Vth
		24.3.4 Multiple Supply Voltages (MSV)
		24.3.5 Dynamic Voltage and Frequency Scaling (DVSF)
		24.3.6 Power Gating (Power Shut Off)
		24.3.7 Isolation Logic
		24.3.8 State Retention
	24.4 Low Power Design Techniques at the RTL Level
	24.5 Low Power Design Architecture and UPF: Case Study [7, 8]
		24.5.1 Isolation cells
		24.5.2 Retention Cells
		24.5.3 Level Shifters
		24.5.4 Power Sequencing and Scheduling
			24.5.4.1 Creation of Power Domains
			24.5.4.2 Create Supply Port
			24.5.4.3 Create Supply Net
			24.5.4.4 Create Power Switch
			24.5.4.5 Connect Supply Net
	24.6 Summary
25 System-On-Chip (SOC) Design
	25.1 What Is System on Chip (SOC)?
	25.2 SOC Architecture
	25.3 SOC Design Flow
		25.3.1 IP Design and Reuse
		25.3.2 SOC Design Considerations
		25.3.3 Hardware–Software Co-design
		25.3.4 Interface Timings
			25.3.4.1 Interface Details and Timing Requirements
			25.3.4.2 Reset Clock Requirements
		25.3.5 EDA Tool and License Requirements
		25.3.6 Prototyping Development
		25.3.7 Test Plan
		25.3.8 Verification Environment
		25.3.9 Prototyping Using FPGAs
			25.3.9.1 ASIC Porting
	25.4 SOC Design Challenges
	25.5 SOC Design Blocks
		25.5.1 Microprocessors or Microcontrollers
		25.5.2 Counters and Timers
		25.5.3 General-Purpose IO Block
		25.5.4 Universal Asynchronous Receiver and Transmitter (UART)
		25.5.5 Bus Arbitration Logic
	25.6 Summary
Appendix I: Important Verilog Keywords
Appendix II: Frequently Used Verilog Constructs
Appendix III: Xilinx Spartan Devices
Bibliography
Index