Digital Design: With an Introduction to the Verilog HDL

Cover......Page 1
Contents......Page 6
Preface......Page 10
 1.1 Digital Systems......Page 18
 1.2 Binary Numbers......Page 20
 1.3 Number-Base Conversions......Page 23
 1.4 Octal and Hexadecimal Numbers......Page 25
 1.5 Complements of Numbers......Page 27
 1.6 Signed Binary Numbers......Page 31
 1.7 Binary Codes......Page 35
 1.8 Binary Storage and Registers......Page 44
 1.9 Binary Logic......Page 47
 2.2 Basic Definitions......Page 55
 2.3 Axiomatic Definition of Boolean Algebra......Page 57
 2.4 Basic Theorems and Properties of Boolean Algebra......Page 60
 2.5 Boolean Functions......Page 63
 2.6 Canonical and Standard Forms......Page 68
 2.7 Other Logic Operations......Page 75
 2.8 Digital Logic Gates......Page 77
 2.9 Integrated Circuits......Page 83
 3.2 The Map Method......Page 90
 3.3 Four-Variable K-Map......Page 97
 3.4 Product-of-Sums Simplification......Page 101
 3.5 Don't-Care Conditions......Page 105
 3.6 NAND and NOR Implementation......Page 107
 3.7 Other Two-Level Implementations......Page 114
 3.8 Exclusive-OR Function......Page 120
 3.9 Hardware Description Language......Page 125
 4.2 Combinational Circuits......Page 142
 4.3 Analysis Procedure......Page 143
 4.4 Design Procedure......Page 146
 4.5 Binary Adder–Subtractor......Page 150
 4.6 Decimal Adder......Page 161
 4.7 Binary Multiplier......Page 163
 4.8 Magnitude Comparator......Page 165
 4.9 Decoders......Page 167
 4.10 Encoders......Page 172
 4.11 Multiplexers......Page 175
 4.12 HDL Models of Combinational Circuits......Page 181
 5.2 Sequential Circuits......Page 207
 5.3 Storage Elements: Latches......Page 210
 5.4 Storage Elements: Flip-Flops......Page 213
 5.5 Analysis of Clocked Sequential Circuits......Page 221
 5.6 Synthesizable HDL Models of Sequential Circuits......Page 234
 5.7 State Reduction and Assignment......Page 248
 5.8 Design Procedure......Page 253
 6.1 Registers......Page 272
 6.2 Shift Registers......Page 275
 6.3 Ripple Counters......Page 283
 6.4 Synchronous Counters......Page 288
 6.5 Other Counters......Page 295
 6.6 HDL for Registers and Counters......Page 300
 7.1 Introduction......Page 316
 7.2 Random-Access Memory......Page 317
 7.3 Memory Decoding......Page 324
 7.4 Error Detection and Correction......Page 329
 7.5 Read-Only Memory......Page 332
 7.6 Programmable Logic Array......Page 338
 7.7 Programmable Array Logic......Page 342
 7.8 Sequential Programmable Devices......Page 346
 8.2 Register Transfer Level Notation......Page 368
 8.3 Register Transfer Level in HDL......Page 371
 8.4 Algorithmic State Machines (ASMs)......Page 380
 8.5 Design Example (ASMD Chart)......Page 388
 8.6 HDL Description of Design Example......Page 398
 8.7 Sequential Binary Multiplier......Page 408
 8.8 Control Logic......Page 413
 8.9 HDL Description of Binary Multiplier......Page 419
 8.10 Design with Multiplexers......Page 428
 8.11 Race-Free Design (Software Race Conditions)......Page 439
 8.12 Latch-Free Design (Why Waste Silicon?)......Page 442
 8.13 Other Language Features......Page 443
 9.1 Introduction to Experiments......Page 455
 9.2 Experiment 1: Binary and Decimal Numbers......Page 460
 9.3 Experiment 2: Digital Logic Gates......Page 463
 9.4 Experiment 3: Simplification of Boolean Functions......Page 465
 9.5 Experiment 4: Combinational Circuits......Page 467
 9.6 Experiment 5: Code Converters......Page 469
 9.7 Experiment 6: Design with Multiplexers......Page 470
 9.8 Experiment 7: Adders and Subtractors......Page 472
 9.9 Experiment 8: Flip-Flops......Page 474
 9.10 Experiment 9: Sequential Circuits......Page 477
 9.11 Experiment 10: Counters......Page 478
 9.12 Experiment 11: Shift Registers......Page 480
 9.13 Experiment 12: Serial Addition......Page 483
 9.14 Experiment 13: Memory Unit......Page 484
 9.15 Experiment 14: Lamp Handball......Page 486
 9.16 Experiment 15: Clock-Pulse Generator......Page 490
 9.17 Experiment 16: Parallel Adder and Accumulator......Page 492
 9.18 Experiment 17: Binary Multiplier......Page 495
 9.19 Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs......Page 497
 10.1 Rectangular-Shape Symbols......Page 505
 10.2 Qualifying Symbols......Page 508
 10.3 Dependency Notation......Page 510
 10.4 Symbols for Combinational Elements......Page 512
 10.5 Symbols for Flip-Flops......Page 514
 10.6 Symbols for Registers......Page 516
 10.7 Symbols for Counters......Page 519
 10.8 Symbol for RAM......Page 521
Appendix......Page 524
Answers to Selected Problems......Page 538
 B......Page 556
 C......Page 557
 F......Page 558
 I......Page 559
 L......Page 560
 R......Page 561
 S......Page 562
 V......Page 563
 X......Page 564