Digital Design: Principles and Practices

1.1 About Digital Design......Page 2
Important Themes in Digital Design......Page 3
1.2 Analog versus Digital......Page 4
1.3 Digital Devices......Page 7
1.4 Electronic Aspects of Digital Design......Page 8
Figure 12 Logic values and noise margins.......Page 9
Figure 13 A logic-design template.......Page 10
Programmable Logic Devices Versus Simulation......Page 12
A Dicey Decision......Page 13
Figure 14 Dual in-line pin (DIP) packages: (a) 14-pin; (b) 20-pin; (c) 28-pin.......Page 14
STANDARD LOGIC FUNCTIONS......Page 15
1.7 Programmable Logic Devices......Page 16
1.8 Application-Specific ICs......Page 17
1.10 Digital-Design Levels......Page 19
Figure 18 Multiplexer design using CMOS transmission gates.......Page 20
Figure 19 Gate-level logic diagram for multiplexer function.......Page 21
Table 12 ABEL program for the multiplexer.......Page 22
1.11 The Name of the Game......Page 23
1.12 Going Forward......Page 24
Drill Problems......Page 25
Number Systems and Codes......Page 26
2.1 Positional Number Systems......Page 27
2.2 Octal and Hexadecimal Numbers......Page 28
Table 21 Binary, decimal, octal, and hexadecimal numbers.......Page 29
2.3 General Positional Number System Conversions......Page 30
Table 22 Conversion methods for common radices.......Page 32
2.4 Addition and Subtraction of Nondecimal Numbers......Page 33
Figure 22 Examples of decimal and corresponding binary subtractions.......Page 34
2.5.1 Signed-Magnitude Representation......Page 35
2.5.3 Radix-Complement Representation......Page 36
Table 25 Digit complements.......Page 37
2.5.4 Two’s-Complement Representation......Page 38
*2.5.6 Ones’-Complement Representation......Page 39
2.6.1 Addition Rules......Page 40
Figure 23 A modular counting representation of 4-bit two’s-complement numbers.......Page 41
2.6.4 Subtraction Rules......Page 42
2.6.5 Two’s-Complement and Unsigned Binary Numbers......Page 43
Figure 24 A modular counting representation of 4-bit unsigned numbers.......Page 44
*2.7 Ones’-Complement Addition and Subtraction......Page 45
*2.8 Binary Multiplication......Page 46
Table 28 Example of long division.......Page 48
2.10 Binary Codes for Decimal Numbers......Page 49
Binomial Coefficients......Page 50
Figure 25 A mechanical encoding disk using a 3-bit binary code.......Page 52
Figure 26 A mechanical encoding disk using a 3-bit Gray code.......Page 53
2.13 Codes for Actions, Conditions, and States......Page 54
Table 211 American Standard Code for Information Interchange (ASCII), Standard No. X3.41968 of.........Page 55
Table 212 States in a traffic-light controller.......Page 56
Figure 27 Control structure for a digital system with n devices: (a) using a binary code; (b) u.........Page 57
Figure 29 Traversing ncubes in Gray-code order: (a) 3cube; (b) 4cube.......Page 58
2.15.1 Error-Detecting Codes......Page 59
Table 213 Distance-2 codes with three information bits.......Page 60
Figure 211 Some code words and noncode words in a 7bit, distance-3 code.......Page 61
2.15.3 Hamming Codes......Page 62
Figure 212 Some code words and noncode words in an 8bit, distance-4 code: (a)correcting 1bit .........Page 63
Figure 213 Parity-check matrices for 7-bit Hamming codes: (a)with bit positions in numerical or.........Page 64
Table 214 Code words in distance-3 and distance-4 Hamming codes with four information bits.......Page 65
2.15.4 CRC Codes......Page 66
Figure 214 Two-dimensional codes: (a)general structure; (b)using even parity for both the row .........Page 67
Figure 215 Structure of error- correcting code for a RAID system.......Page 68
2.15.7 m-out-of-n Codes......Page 69
Figure 216 Basic concepts for serial data transmission.......Page 70
Figure 217 Commonly used line codes for serial data.......Page 71
Kilo-, Mega-, Giga-, Tera-......Page 73
References......Page 74
Drill Problems......Page 75
Exercises......Page 77
Digital Circuits......Page 80
3.1 Logic Signals and Gates......Page 81
Figure 31 “Black box” representation of a three-input, one-output logic circuit.......Page 82
Figure 32 Basic logic elements: (a) AND; (b) OR; (c) NOT(inverter).......Page 83
Figure 34 Logic circuit with the truth table of Table32.......Page 84
3.2 Logic Families......Page 85
Green Stuff......Page 86
3.3.2 MOS Transistors......Page 87
Figure 39 Circuit symbol for a p-channel MOS (PMOS) transistor.......Page 88
Figure 310 CMOS inverter: (a) circuit diagram; (b) functional behavior; (c) logic symbol.......Page 89
Figure 312 CMOS inverter logical operation.......Page 90
Figure 313 CMOS 2-input NAND gate: (a) circuit diagram; (b) function table; (c) logic symbol.......Page 91
Figure 315 CMOS 2-input NOR gate: (a) circuit diagram; (b) function table; (c) logic symbol.......Page 92
Figure 317 Logic diagram equivalent to the internal structure of an 8-input CMOS NAND gate.......Page 93
Figure 319 CMOS 2-input AND gate: (a) circuit diagram; (b) function table; (c) logic symbol.......Page 94
Figure 321 Logic diagram for CMOS AND-OR-INVERT gate.......Page 95
Figure 323 Logic diagram for CMOS OR-AND-INVERT gate.......Page 96
3.4.1 Overview......Page 97
Don’t Be Afraid......Page 98
What’s in a Number?......Page 99
3.5.1 Logic Levels and Noise Margins......Page 100
Figure 325 Typical input-output transfer characteristic of a CMOS inverter.......Page 101
Figure 326 Logic levels and noise margins for the HC-series CMOS logic family.......Page 102
Figure 327 Resistive model of a CMOS inverter with a resistive load: (a) showing actual load ci.........Page 103
Figure 328 Resistive model for CMOS LOW output with resistive load.......Page 104
Figure 329 Resistive model for CMOS HIGH output with resistive load.......Page 105
Table 34 Output loading specifications for HC-series CMOS with a 5-volt supply.......Page 106
3.5.3 Circuit Behavior with Nonideal Inputs......Page 108
Figure 332 CMOS inverter with nonideal input voltages: (a) equivalent circuit with 1.5-V input;.........Page 109
3.5.4 Fanout......Page 110
3.5.5 Effects of Loading......Page 111
Subtle Bugs......Page 112
3.5.8 How to Destroy a CMOS Device......Page 113
3.6 CMOS Dynamic Electrical Behavior......Page 114
Figure 336 Transition times: (a) ideal case of zero-time switching; (b) a more realistic approxi.........Page 115
Figure 337 Equivalent circuit for analyzing transition times of a CMOS output.......Page 116
Figure 338 Model of a CMOS HIGH-to-LOW transition: (a) in the HIGH state; (b) after p-channel t.........Page 117
Figure 340 Model of a CMOS LOW-to-HIGH transition: (a) in the LOW state; (b) after n-channel tr.........Page 118
Figure 341 Rise time for a LOW- to-HIGH transition of a CMOS output.......Page 119
3.6.2 Propagation Delay......Page 120
Figure 343 Worst-case timing specified using logic- level boundary points.......Page 121
3.6.3 Power Consumption......Page 122
Figure 345 Two-input multiplexer using CMOS transmission gates.......Page 124
Figure 346 A Schmitt-trigger inverter: (a) input- output transfer characteristic; (b) logic symbol.......Page 125
Fixing Your Transmission......Page 126
Figure 348 CMOS three-state buffer: (a) circuit diagram; (b) function table; (c) logic symbol.......Page 127
*3.7.4 Open-Drain Outputs......Page 128
Figure 350 Open-drain CMOS NAND gate driving a load.......Page 129
Figure 352 Driving an LED with an open-drain output.......Page 130
Resistor Values......Page 131
Figure 354 Eight open-drain outputs driving a bus.......Page 132
Figure 355 Wired-AND function on three open-drain NAND-gate outputs.......Page 133
*3.7.8 Pull-Up Resistors......Page 134
Figure 358 Four open-drain outputs driving two inputs in the HIGH state.......Page 135
3.8 CMOS Logic Families......Page 136
Figure 360 Transfer characteristics of HC and HCT circuits under typical conditions.......Page 137
3.8.3 HC, HCT, VHC, and VHCT Electrical Characteristics......Page 138
Note on Notation......Page 139
Saving Energy......Page 140
CMOS vs. TTL Power Dissipation......Page 141
Table 37 Output specifications for CMOS families operating with VCC between 4.5 and 5.5V.......Page 142
*3.8.4 FCT and FCT-T......Page 143
*3.8.5 FCT-T Electrical Characteristics......Page 144
Table 38 Specifications for a 74FCT138T decoder in the FCT-T logic family.......Page 145
Figure 361 Semiconductor diodes: (a) the pn junction; (b) forward-biased junction allowing curr.........Page 146
Yes, There Are Two Arrows......Page 147
Zener Diodes......Page 148
Figure 364 Diode AND gate: (a) electrical circuit; (b) both inputs HIGH; (c) one input HIGH, one.........Page 149
3.9.3 Bipolar Junction Transistors......Page 150
Figure 366 Development of an npn transistor: (a) back-to-back diodes; (b) equivalent pn junctio.........Page 151
Figure 368 Common-emitter configuration of an npn transistor.......Page 152
Figure 370 Normal states of an npn transistor in a digital switching circuit: (a) transistor sy.........Page 154
Figure 369 Transistor inverter: (a) logic symbol; (b) circuit diagram; (c) transfer characteristic.......Page 153
3.9.5 Schottky Transistors......Page 155
Figure 374 Inverter using Schottky transistor.......Page 156
Where in the World is Q1?......Page 157
Figure 376 Functional operation of a TTL two-input NAND gate: (a) function table; (b) truth tabl.........Page 158
3.10.2 Logic Levels and Noise Margins......Page 159
Figure 378 A TTL output driving a TTL input HIGH.......Page 160
3.10.3 Fanout......Page 161
TTL Output Asymmetry......Page 162
3.10.4 Unused Inputs......Page 163
Figure 381 Pull-up resistor for TTL inputs.......Page 164
3.10.5 Additional TTL Gate Types......Page 165
Figure 383 Two-input LS-TTL NOR gate: (a) function table; (b) truth table; (c) logic symbol.......Page 166
3.11.2 Schottky TTL Families......Page 167
3.11.3 Characteristics of TTL Families......Page 168
3.11.4 A TTL Data Sheet......Page 169
Table 312 Typical manufacturer’s data sheet for the 74LS00.......Page 170
Figure 384 Output and input levels for interfacing TTL and CMOS families. (Note that HC and VHC .........Page 171
*3.13 Low-Voltage CMOS Logic and Interfacing......Page 172
Figure 385 Comparison of logic levels: (a) 5-V CMOS; (b) 5-V TTL, including 5-V TTL-compatible .........Page 173
Figure 386 CMOS input structures: (a) non-5-V tolerant HC; (b) 5-V tolerant VHC.......Page 174
Figure 387 CMOS three-state output structures: (a) non-5-V tolerant HC and VHC; b) 5-V tolerant .........Page 175
*3.14 Emitter-Coupled Logic......Page 176
Figure 388 Basic CML inverter/buffer circuit with input HIGH.......Page 177
Figure 389 Basic CML inverter/buffer circuit with input LOW.......Page 178
Figure 390 CML 2-input OR/NOR gate: (a) circuit diagram; (b) function table; (c) logic symbol;.........Page 179
*3.14.2 ECL 10K/10H Families......Page 180
Figure 391 ECL 10K logic levels.......Page 181
Figure 392 Two-input 10K ECL OR/NOR gate: (a) circuit diagram; (b) function table; (c) truth ta.........Page 182
*3.14.4 Positive ECL (PECL)......Page 183
References......Page 184
Drill Problems......Page 185
Exercises......Page 189
Combinational Logic Design Principles......Page 196
4.1 Switching Algebra......Page 197
4.1.1 Axioms......Page 198
Note on Notation......Page 199
Juxt a Minute…......Page 200
4.1.3 Two- and Three-Variable Theorems......Page 201
Table 42 Switching-algebra theorems with two or three variables.......Page 202
4.1.4 n-Variable Theorems......Page 203
Figure 43 Equivalent circuits according to DeMorgan’s theorem T13: (a) AND-NOT; (b) NOT-OR; (c).........Page 204
Figure 44 Equivalent circuits according to DeMorgan’s theorem T13¢: (a) OR-NOT; (b) NOT-AND; (c.........Page 205
4.1.5 Duality......Page 206
Figure 46 A “type-2” logic gate: (a) electrical function table; (b) logic function table and sy.........Page 207
Figure 48 Negative-logic interpretation of the previous circuit.......Page 208
Table 44 t General truth table structure for a 3-variable logic function, F(X,Y,Z).......Page 209
Table 45 Truth table for a particular 3-variable logic function, F(X,Y,Z).......Page 210
Table 46 Minterms and maxterms for a 3-variable logic function, F(X,Y,Z).......Page 211
4.2 Combinational Circuit Analysis......Page 212
A Less Exhausting Way to Go......Page 213
Figure 411 Logic expressions for signal lines.......Page 214
Figure 413 Two-level OR-AND circuit.......Page 215
Figure 415 Algebraic analysis of the previous circuit after substituting some NAND and NOR symbols.......Page 216
Figure 417 Three circuits for G(W, X, Y, Z) = W × X ×Y + Y × Z: (a) two-level AND-OR; (b) two-l.........Page 217
Figure 418 Canonical-sum design for 4-bit prime-number detector.......Page 218
Figure 420 Sum-of-products version of alarm circuit.......Page 219
Figure 421 Alternative sum-of- products realizations: (a) AND-OR; (b) AND-OR with extra inverter.........Page 220
Figure 423 Realizations of a product-of-sums expression: (a) OR-AND; (b) OR-AND with extra inver.........Page 221
Figure 424 Logic-symbol manipulations: (a) original circuit; (b) transformation with a nonstand.........Page 222
Why Minimize?......Page 223
4.3.4 Karnaugh Maps......Page 224
4.3.5 Minimizing Sums of Products......Page 225
Figure 427 F = SX,Y,Z(1,2,5,7): (a) truth table; (b) Karnaugh map; (c) combining adjacent 1-cells.......Page 226
Figure 428 Minimized AND-OR circuit.......Page 227
Figure 429 F = SX,Y,Z(0,1,4,5,6): (a) initial Karnaugh map; (b) Karnaugh map with circled produc.........Page 228
Figure 430 Prime-number detector: (a) initial Karnaugh map; (b) circled product terms; (c) mini.........Page 229
Figure 432 F = SW,X,Y,Z(1,3,4,5,9,11,12,13,14,15): (a) Karnaugh map; (b) prime implicants and d.........Page 230
Figure 433 F =SW,X,Y,Z(2,3,4,5,6,7,11,13,15): (a) Karnaugh map; (b) prime implicants and distin.........Page 231
Figure 435 F = SW,X,Y,Z(2,6,7,9,13,15): (a) Karnaugh map; (b) prime implicants and distinguishe.........Page 232
4.3.6 Simplifying Products of Sums......Page 233
PLD Minimization......Page 234
Figure 437 Prime BCD-digit detector: (a) initial Karnaugh map; (b) Karnaugh map with prime impl.........Page 235
Figure 438 Treating a 2-output design as two independent single-output designs: (a) Karnaugh ma.........Page 236
Figure 439 Multiple-output minimization for a 2-output circuit: (a) minimized maps including a .........Page 237
Figure 440 Karnaugh maps for a set of two functions: (a) maps for F and G; (b) 2-product map fo.........Page 238
*4.4.1 Representation of Product Terms......Page 239
Figure 442 Cube manipulations: (a) determining whether two cubes are combinable using theorem T.........Page 241
Table 48 Cube comparing and combining functions used in minimization program.......Page 242
*4.4.2 Finding Prime Implicants by Combining Product Terms......Page 243
Table 49 A C program that finds prime implicants using the Quine-McCluskey algorithm.......Page 244
Figure 443 Prime-implicant tables: (a) original table; (b) showing distinguished 1-cells and es.........Page 245
*4.4.4 Other Minimization Methods......Page 246
*4.5.1 Static Hazards......Page 247
*4.5.2 Finding Static Hazards Using Maps......Page 248
Figure 4-46 Karnaugh map for the circuit of Figure444: (a) as originally designed; (b) with sta.........Page 249
*4.5.3 Dynamic Hazards......Page 250
*4.5.4 Designing Hazard-Free Circuits......Page 251
4.6.1 ABEL Program Structure......Page 252
Table 410 Typical structure of an ABEL program.......Page 253
Table 411 An ABEL program for the alarm circuit of Figure411.......Page 254
4.6.2 ABEL Compiler Operation......Page 255
Table 413 Structure of an ABEL WHEN statement.......Page 256
Table 414 Examples of WHEN statements.......Page 258
Table 415 Synthesized equations file produced by ABEL for program in Table414.......Page 259
Table 417 An ABEL program for the prime number detector.......Page 260
4.6.5 Ranges, Sets, and Relations......Page 261
Table 419 Relational operators in ABEL.......Page 262
*4.6.6 Don’t-Care Inputs......Page 263
Table 422 Minimized equations derived from Table421.......Page 264
4.6.7 Test Vectors......Page 265
Table 425 Single-stuck-at-fault test vectors for the minimal sum-of- products realization of the.........Page 266
Figure 450 A 4-variable Veitch diagram or Marquand chart.......Page 267
Drill Problems......Page 269
Exercises......Page 271
Combinational Logic Design Practices......Page 278
5.1 Documentation Standards......Page 279
Documents OnLine......Page 280
Figure 51 Block diagram for a digital design project.......Page 281
Figure 52 A 32-bit register block: (a)realization unspecified; (b)chips specified; (c)too muc.........Page 282
IEEE Standard Logic Symbols......Page 283
5.1.3 Signal Names and Active Levels......Page 284
Table 51 Each line shows a different naming convention for active levels.......Page 285
Figure 56 Four ways of obtaining an AND function: (a) AND gate (74x08); (b) NAND gate (74x00); .........Page 286
5.1.5 Bubble-to-Bubble Logic Design......Page 287
Figure 510 Two more ways to GO, with mixed input levels: (a) with an AND gate; (b) with a NOR g.........Page 288
Figure 512 Another properly drawn logic diagram.......Page 289
5.1.6 Drawing Layout......Page 290
Figure 514 Flat schematic structure.......Page 291
Figure 515 Hierarchical schematic structure.......Page 292
5.1.7 Buses......Page 293
Figure 516 Examples of buses.......Page 294
Figure 517 Schematic diagram for a circuit using a 74HCT00.......Page 295
Figure 518 Pinouts for SSI ICs in standard dual-inline packages.   ......Page 296
5.2.1 Timing Diagrams......Page 297
Figure 519 Timing diagrams for a combinational circuit: (a) block diagram of circuit; (b) causa.........Page 298
5.2.2 Propagation Delay......Page 299
How Typical Is Typical?......Page 300
A Corollary of Murphy’s Law......Page 301
Table 53 Propagation delay in nanoseconds of selected CMOS and TTL MSI parts.......Page 302
5.2.4 Timing Analysis......Page 303
5.3.1 Programmable Logic Arrays......Page 304
Figure 522 Compact representation of a 4 ¥ 3 PLA with six product terms.......Page 305
Figure 524 A 4 ¥ 3 PLA programmed to produce constant 0 and 1 outputs.......Page 306
Friends and Foes......Page 307
Figure 525 Logic diagram of the PAL16L8.......Page 308
Figure 526 Traditional logic symbol for the PAL16L8.......Page 309
5.3.3 Generic Array Logic Devices......Page 310
CombinationAl PLD Speed......Page 311
Figure 527 Logic diagram of the GAL16V8C.......Page 312
Figure 528 A 4 ¥ 3 PLA built using TTL-like open-collector gates and diode logic.......Page 313
Figure 529 A 4 ¥ 3 PLA built using CMOS logic.......Page 314
Figure 530 AND plane of an EPLD using floating- gate MOS transistors.......Page 315
*5.3.6 Device Programming and Testing......Page 316
Figure 531 Decoder circuit structure.......Page 318
Figure 532 A 2-to-4 decoder: (a) inputs and outputs; (b) logic diagram.......Page 319
5.4.2 Logic Symbols for Larger-Scale Elements......Page 320
Figure 534 Logic symbol for one-half of a 74x139 dual 2-to-4 decoder: (a) conventional symbol; (.........Page 321
Figure 535 The 74x139 dual 2-to-4 decoder: (a) logic diagram, including pin numbers for a stand.........Page 322
Figure 536 More ways to symbolize a 74x139: (a) correct but to be avoided; (b) incorrect because.........Page 323
5.4.4 The 74x138 3-to-8 Decoder......Page 324
5.4.6 Decoders in ABEL and PLDs......Page 325
Figure 538 Design of a 4-to-16 decoder using 74x138s.......Page 326
Figure 539 Design of a 5-to-32 decoder using 74x138s and a 74x139.......Page 327
Figure 540 Logic diagram for the PAL16L8 used as a 74x138 decoder.......Page 328
Table 510 Truth table for a customized decoder function.......Page 330
Table 511 ABEL equations for a customized decoder.......Page 331
5.4.7 Decoders in VHDL......Page 332
Table 514 Dataflow-style VHDL program for a 74x138-like 3-to-8 binary decoder.......Page 333
Out-of-Order Execution......Page 334
Table 517 Dataflow definition of an active-high 3-to-8 decoder.......Page 335
Table 518 Behavioral-style architecture definition for a 3-to-8 decoder.......Page 336
Figure 543 Seven-segment display: (a) segment identification; (b) decimal digits.......Page 337
Table 520 Truth table for a 74x49 seven-segment decoder.......Page 339
Figure 544 The 74x49 seven-segment decoder: (a) logic diagram, including pin numbers; (b) tradi.........Page 338
Table 521 ABEL program for a 74x49-like seven-segment decoder.......Page 340
5.5.1 Priority Encoders......Page 341
Figure 547 Logic symbol for a generic 8-input priority encoder.......Page 342
Table 522 Truth table for a 74x148 8-input priority encoder.......Page 343
Figure 549 Logic diagram for the 74x148 8-input priority encoder, including pin numbers for a s.........Page 344
Figure 550 Four 74x148s cascaded to handle 32 requests.......Page 345
Figure 551 Logic diagram for a PLD-based 15-input priority encoder......Page 346
Table 523 An ABEL program for a 15-input priority encoder.......Page 347
5.5.4 Encoders in VHDL......Page 348
Table 525 Behavioral VHDL program for a 74x148-like 8-input priority encoder.......Page 349
Defining “Undefined”......Page 350
Figure 553 Eight sources sharing a three-state party line.......Page 351
Figure 555 Pinouts of the 74x125 and 74x126 three- state buffers.......Page 352
Figure 557 Using a 74x541 as a microprocessor input port.......Page 353
Figure 558 The 74x245 octal three-state transceiver: (a) logic diagram; (b) traditional logic sy.........Page 354
Figure 559 Bidirectional buses and transceiver operation.......Page 355
5.6.3 Three-State Outputs in ABEL and PLDs......Page 356
Table 528 Bus selection codes for a four-way bus transceiver.......Page 357
Table 529 An ABEL program for four-way, 2-bit bus transceiver.......Page 358
Table 530 IEEE 1164 package declarations for STD_ULOGIC and STD_LOGIC.......Page 359
*5.6.4 Three-State Outputs in VHDL......Page 360
Table 532 VHDL program with four 8-bit three-state drivers.......Page 362
Figure 561 Multiplexer structure: (a) inputs and outputs; (b) functional equivalent.......Page 363
Figure 562 The 74x151 8-input, 1-bit multiplexer: (a) logic diagram, including pin numbers for a.........Page 364
Figure 563 The 74x157 2-input, 4-bit multiplexer: (a) logic diagram, including pin numbers for .........Page 365
Figure 564 Traditional logic symbol for the 74x153.......Page 366
Control-Signal Fanout in ASICS......Page 367
Figure 565 Combining 74x151s to make a 32-to-1 multiplexer.......Page 368
Figure 566 A multiplexer driving a bus and a demultiplexer receiving the bus: (a) switch equival.........Page 369
5.7.4 Multiplexers in ABEL and PLDs......Page 370
Table 536 ABEL program for a 74x153-like 4-input, 2-bit multiplexer.......Page 371
Table 538 ABEL program for a 4-input, 8-bit multiplexer.......Page 372
Figure 569 Logic diagram for the PAL16L8 used as a specialized 4-input, 3-bit multiplexer.......Page 373
Easiest, but not Cheapest......Page 374
5.8.1 EXCLUSIVE OR and EXCLUSIVE NOR Gates......Page 375
Table 544 Truth table for XOR and XNOR functions.......Page 376
Figure 572 Pinouts of the 74x86 quadruple 2-input Exclusive OR gate.......Page 377
5.8.4 Parity-Checking Applications......Page 378
Speeding up the XOR Tree......Page 379
Figure 575 Parity generation and checking for an 8-bit-wide memory system.......Page 380
Figure 576 Error-correcting circuit for a 7-bit Hamming code.......Page 381
Table 545 Dataflow-style VHDL program for a 3-input XOR device.......Page 382
Table 546 Behavioral VHDL program for a 9-input parity checker.......Page 383
5.9 Comparators......Page 384
5.9.1 Comparator Structure......Page 385
5.9.2 Iterative Circuits......Page 386
5.9.3 An Iterative Comparator Circuit......Page 387
Figure 580 Traditional logic symbol for the 74x85 4-bit comparator.......Page 388
Figure 582 Traditional logic symbol for the 74x682 8-bit comparator.......Page 389
Figure 583 Logic diagram for the 74x682 8-bit comparator, including pin numbers for a standard .........Page 390
5.9.5 Comparators in ABEL and PLDs......Page 391
5.9.6 Comparators in VHDL......Page 392
Table 549 Behavioral VHDL program for comparing 8-bit unsigned integers.......Page 393
*5.10 Adders, Subtractors, and ALUs......Page 395
Figure 585 Full adder: (a) gate- level circuit diagram; (b) logic symbol; (c) alternate logic sy.........Page 396
*5.10.3 Subtractors......Page 397
*5.10.4 Carry Lookahead Adders......Page 399
Figure 588 Structure of one stage of a carry lookahead adder.......Page 400
Figure 589 Traditional logic symbol for the 74x283 4-bit binary adder.......Page 401
Figure 590 Logic diagram for the 74x283 4-bit binary adder.......Page 402
Figure 591 A 16-bit group-ripple adder.......Page 403
Table 551 Functions performed by the 74x181 4-bit ALU.......Page 404
Figure 593 Logic symbols for 4-bit ALUs: (a) 74x381; (b) 74x382.......Page 405
Figure 594 Logic symbol for the 74x182 lookahead carry circuit.......Page 406
Figure 595 A 16-bit ALU using group-carry lookahead.......Page 407
Table 553 ABEL program for an 8-bit adder.......Page 408
*5.10.9 Adders in VHDL......Page 409
Table 554 VHDL program for adding and subtracting 8-bit integers of various types.......Page 410
Figure 596 Partial products in an 8 ¥ 8 multiplier.......Page 411
Figure 597 Interconnections for an 8 ¥ 8 combinational multiplier.......Page 412
Figure 598 Interconnections for a faster 8 ¥ 8 combinational multiplier.......Page 413
Table 556 ABEL program for a 4¥4 combinational multiplier.......Page 414
Figure 599 VHDL variable names for the 8 ¥ 8 multiplier.......Page 415
Table 557 Behavioral VHDL program for an 8¥8 combinational multiplier.......Page 416
On the Threshold of a Dream......Page 417
Table 558 Structural VHDL architecture for an 8¥8 combinational multiplier.......Page 418
References......Page 419
Synthesis of Behavioral Designs......Page 420
Drill Problems......Page 421
Exercises......Page 424
Combinational Design Examples......Page 434
6.1.1 Barrel Shifter......Page 435
Table 61 Properties of four different barrel-shifter design approaches.......Page 436
Figure 62 A second approach to building a 16-bit barrel shifter.......Page 437
6.1.2 Simple Floating-Point Encoder......Page 438
Figure 63 A combinational fixed-point to floating- point encoder. ......Page 439
Figure 64 Alternate logic symbol for the 74x151 8-input multiplexer.......Page 440
Figure 65 Alternate logic symbols for the 74x148 8-input priority encoder.......Page 441
Figure 66 First-and second-highest priority encoder circuit. ......Page 442
6.1.5 Mode-Dependent Comparator......Page 443
Figure 67 24-bit comparator circuit.......Page 444
Figure 68 Mode-dependent comparator circuit: (a) block diagram of a “first-cut” solution; (b) b.........Page 445
6.2.1 Barrel Shifter......Page 446
Table 62 ABEL program for a 16-bit barrel shifter.......Page 447
Table 64 An ABEL program for the fixed-point to floating-point PLD.......Page 449
Table 65 Alternative ABEL program for the fixed-point to floating-point PLD.......Page 450
Table 66 ABEL program for a dual priority encoder.......Page 451
Sums of Products and Products of Sums (Say That 5 Times Fast)......Page 452
6.2.4 Cascading Comparators......Page 453
Table 68 ABEL program for combining eight 74x682s into a 64-bit comparator.......Page 454
Table 610 Product-term usage for the MODECOMP PLD.......Page 455
Figure 69 A 32-bit mode-dependent comparator.......Page 456
6.2.6 Ones Counter......Page 457
Table 612 ABEL program for counting the 1 bits in a 15-bit word.......Page 458
Tic-Tac-Toe, In Case You Didn’t Know......Page 459
Figure 611 Tic-Tac-Toe grid and ABEL signal names.......Page 460
Table 613 ABEL program to find two in a row in Tic-Tac-Toe.......Page 461
Table 613 (continued)......Page 462
Table 614 Product-term usage for the TWOINROW PLD.......Page 463
Figure 613 Final PLD partitioning for the Tic-Tac-Toe game.......Page 464
6.3.1 Barrel Shifter......Page 467
Rolling Your Own......Page 469
Figure 614 Barrel-shifter components.......Page 472
A Serial Fix-Up Structure......Page 473
6.3.2 Simple Floating-Point Encoder......Page 475
Table 624 Alternative VHDL architecture for fixed-point to floating- point conversion.......Page 476
Gobble, Gobble......Page 477
6.3.3 Dual-Priority Encoder......Page 478
Table 626 Behavioral VHDL program for a dual priority encoder.......Page 479
6.3.4 Cascading Comparators......Page 480
Table 629 VHDL program for an 8-bit comparator.......Page 481
6.3.5 Mode-Dependent Comparator......Page 482
6.3.6 Ones Counter......Page 483
Table 633 Behavioral VHDL program for a 32-bit ones counter.......Page 484
Figure 615 Structure of 32-bit ones counter.......Page 485
Table 634 VHDL structural architecture for a 32-bit ones counter.......Page 486
6.3.7 Tic-Tac-Toe......Page 487
Figure 616 Tic-Tac-Toe grid and VHDL signal names.......Page 488
Figure 617 Entity partitioning for the Tic-Tac-Toe game.......Page 489
Table 638 Declaration of TwoInRow entity.......Page 490
Table 639 (continued)......Page 492
Table 640 VHDL program to pick a winning or blocking Tic-Tac-Toe move, or else use “experience.”......Page 493
Exercises......Page 494
Sequential Logic Design Principles......Page 496
Non-Finite- State Machines......Page 497
7.1.1 Digital Analysis......Page 498
Figure 73 Transfer functions for inverters in a bistable feedback loop.......Page 499
Figure 74 Ball and hill analogy for metastable behavior.......Page 500
7.2 Latches and Flip-Flops......Page 501
Figure 76 Typical operation of an S-R latch: (a) “normal” inputs; (b) S and R asserted simultan.........Page 502
Figure 77 Symbols for an S-R latch: (a) without bubble; (b) preferred for bubble- to-bubble desi.........Page 503
Figure 79 S-R latch: (a) circuit design using NAND gates; (b) function table; (c) logic symbol.......Page 504
7.2.4 D Latch......Page 505
Figure 714 Timing parameters for a D latch.......Page 506
Figure 715 Positive-edge-triggered D flip-flop: (a) circuit design using D latches; (b) functio.........Page 507
Figure 717 Timing behavior of a positive-edge-triggered D flip-flop.......Page 508
7.2.6 Edge-Triggered D Flip-Flop with Enable......Page 509
7.2.7 Scan Flip-Flop......Page 510
Figure 723 A scan chain with four flip-flops.......Page 511
Figure 724 Master/slave S-R flip-flop: (a) circuit using S-R latches; (b) function table; (c) l.........Page 512
Figure 726 Master/slave J-K flip-flop: (a) circuit design using S-R latches; (b) function table.........Page 513
Figure 728 Edge-triggered J-K flip-flop: (a) equivalent function using an edge-triggered D flip.........Page 514
Figure 730 Internal logic diagram for the 74LS109 positive-edge-triggered J-K flip-flop.......Page 515
Figure 733 Positive-edge-triggered T flip-flop with enable: (a) logic symbol; (b) functional be.........Page 516
Figure 735 Clocked synchronous state-machine structure (Mealy machine).......Page 517
7.3.2 Output Logic......Page 518
7.3.3 Characteristic Equations......Page 519
7.3.4 Analysis of State Machines with D Flip-Flops......Page 520
Figure 738 Clocked synchronous state machine using positive-edge-triggered D flip-flops.......Page 521
Table 72 Transition, state, and state/output tables for the state machine in Figure738.......Page 522
Table 73 State/output table for a Moore machine.......Page 523
Little Arrows, Little Arrows Everywhere......Page 524
Figure 742 Timing diagram for example state machine.......Page 525
Figure 743 A clocked synchronous state machine with three flip-flops and eight states.......Page 526
Figure 744 State diagram corresponding to Table74.......Page 527
Figure 745 Clocked synchronous state machine using J-K flip-flops.......Page 528
Figure 746 State diagram corresponding to the state machine of Table75.......Page 529
7.4 Clocked Synchronous State-Machine Design......Page 530
State-Table Design as a Kind of Programming......Page 531
Figure 747 Timing diagram for example state machine.......Page 532
Figure 748 Evolution of a state table.......Page 533
Figure 749 Continued evolution of a state table.......Page 534
Figure 751 Nonminimal state tables equivalent to Figure749(d).......Page 535
Initial Versus Idle States......Page 536
Caution: Math......Page 537
Table 77 Possible state assignments for the state machine in Table76.......Page 538
Table 78 Transition and output table for example problem.......Page 540
Figure 752 Excitation maps for D1, D2, and D3 assuming that unused states go to state 000.......Page 541
Minimal-Cost Solution......Page 542
*7.4.5 Synthesis Using J-K Flip-Flops......Page 543
Table 710 Application table for JK flip-flops.......Page 544
Figure 755 Excitation maps for J1, K1, J2, K2, J3, and K3, assuming that unused states go to st.........Page 545
Minimal-Cost Solution......Page 546
Table 712 State and output table for 1s-counting machine.......Page 547
Figure 757 Excitation maps for D1 and D2 inputs in 1s-counting machine.......Page 548
Table 714 State and output table for combination-lock machine.......Page 549
Figure 758 Excitation maps for D1, D2, and D3 in combination-lock machine.......Page 550
7.5 Designing State Machines Using State Diagrams......Page 551
Whose Rear End?......Page 552
Figure 762 Initial state diagram and output table for T-bird tail lights.......Page 553
Figure 763 Corrected state diagram for T-bird tail lights.......Page 555
Figure 764 Enhanced state diagram for T-bird tail lights.......Page 556
Table 716......Page 557
*7.6.1 Transition Equations......Page 558
*7.6.3 Variations on the Scheme......Page 560
*7.7.1 The Guessing Game......Page 561
Figure 765 First try at a state diagram for the guessing game.......Page 562
Table 718 Transition list for guessing-game machine.......Page 564
*7.7.3 Output-Coded State Assignment......Page 565
Table 719 ......Page 566
Table 720......Page 567
Table 721 ......Page 568
A REALLY BAD JOKE......Page 569
Figure 770 State diagram for guessing machine with enable.......Page 570
*7.9.1 Analysis......Page 571
Figure 771 Feedback sequential circuit structure for Mealy and Moore machines.......Page 572
Just One Loop......Page 573
Figure 775 State and output table for the D latch.......Page 574
Figure 777 Multiple input changes with the D latch.......Page 575
*7.9.2 Analyzing Circuits with Multiple Feedback Loops......Page 576
Figure 779 Transition table for the D flip-flop in Figure778.......Page 577
Watch Out for Critical Races!......Page 578
Figure 782 State/output table for the D flip-flop in Figure778.......Page 579
Figure 784 Flow and output table showing the D flip-flop’s edge-triggered behavior.......Page 580
*7.9.5 CMOS D Flip-Flop Analysis......Page 581
*7.10.1 Latches......Page 582
Figure 788 Latch circuits: (a) S-R latch; (b) unreliable D latch; (c) hazard-free D latch.......Page 583
*7.10.2 Designing Fundamental-Mode Flow Table......Page 584
Figure 790 Typical functional behavior of a pulse-catching circuit.......Page 585
*7.10.3 Flow-Table Minimization......Page 586
Figure 793 Example flow table for the state-assignment problem.......Page 587
Figure 795 Adjacency diagrams for the pulse catcher: (a) using original flow table; (b) after a.........Page 588
Figure 797 A worst-case scenario: (a) 4-state adjacency diagram; (b) assignment using pairs of e.........Page 589
Figure 799 Karnaugh maps for pulse-catcher excitation and output logic.......Page 590
*7.10.6 Essential Hazards......Page 591
Figure 7101 Physical conditions in pulse-catching circuit for exhibiting an essential hazard.......Page 592
These Hazards Are, Well, Essential!......Page 593
7.11.1 Registered Outputs......Page 594
Is istype Essential?......Page 595
7.11.2 State Diagrams......Page 596
Table 724 Structure of an ABEL IF statement.......Page 597
Table 725 An example of ABEL’s state-diagram notation.......Page 598
Use It or ELSE......Page 599
Phantom (of the) Operand......Page 600
*7.11.3 External State Memory......Page 601
Table 729 State machine with embedded Moore output definitions.......Page 602
Table 730 Structure of ABEL WITH statement.......Page 603
Table 731 State machine with embedded Mealy output definitions.......Page 604
7.11.6 Test Vectors......Page 605
Table 733 ABEL program with test vectors for a simple 8-bit register.......Page 606
Synchronizing Sequences and Reset Inputs......Page 607
Table 735 Test vectors for the combination-lock state machine of Table731.......Page 608
References......Page 609
Drill Problems......Page 610
Exercises......Page 614
Sequential Logic Design Practices......Page 624
8.1.2 Logic Symbols......Page 625
8.1.3 State-Machine Descriptions......Page 626
Figure 81 A detailed timing diagram showing propagation delays and setup and hold times with res.........Page 627
Figure 82 Functional timing of a synchronous circuit.......Page 628
Table 81 (continued)Propagation delay in ns of selected CMOS flip-flops, registers, and latches.......Page 629
8.2.1 SSI Latches and Flip-Flops......Page 631
*8.2.2 Switch Debouncing......Page 632
*8.2.3 The Simplest Switch Debouncer......Page 633
Where Wimpy Works Well......Page 634
Figure 87 Bus holder circuit.......Page 635
Figure 88 The 74x175 4-bit register: (a) logic diagram, including pin numbers for a standard 16-.........Page 636
Figure 810 The 74x374 8-bit register: (a) logic diagram, including pin numbers for a standard 20.........Page 637
Figure 813 The 74x377 8-bit register with gated clock: (a) logic symbol; (b) logical behavior o.........Page 638
8.2.6 Registers and Latches in ABEL and PLDs......Page 639
Figure 815 Microprocessor address latching and decoding circuit.......Page 640
Figure 816 Using a combined address latching and decoding circuit.......Page 641
8.2.7 Registers and Latches in VHDL......Page 642
Table 84 VHDL behavioral architecture for a D latch.......Page 643
Table 86 VHDL behavioral model of an edge-triggered D flip-flop.......Page 644
Table 88 VHDL model of a 16-bit register with many features.......Page 645
8.3.1 Bipolar Sequential PLDs......Page 646
Figure 817 PAL16R8 logic diagram.......Page 648
Figure 818 PAL16R6 logic diagram.......Page 649
Table 89 Characteristics of standard bipolar PLDs.......Page 647
8.3.2 Sequential GAL Devices......Page 650
Figure 820 Logic diagram for the 16V8 in the “registered” configuration.......Page 651
Figure 821 Output logic macrocells for the 16V8R: (a) registered; (b) combinational.......Page 652
Figure 822 Logic diagram for the 22V10.......Page 653
Figure 823 Output logic macrocells for the 22V10: (a) registered; (b) combinational.......Page 654
8.3.3 PLD Timing Specifications......Page 655
Figure 825 PLD timing parameters.......Page 656
Table 810 Timing specifications, in nanoseconds, of popular bipolar and CMOS PLDs. ......Page 657
Figure 826 General structure of a counter’s state diagram—a single cycle.......Page 658
8.4.2 Synchronous Counters......Page 659
Figure 829 A synchronous 4-bit binary counter with parallel enable logic......Page 660
Table 811 State table for a 74x163 4-bit binary counter.......Page 661
Figure 831 Logic diagram for the 74x163 synchronous 4-bit binary counter, including pin numbers.........Page 662
Figure 833 Clock and output waveforms for a free-running divide-by-16 counter.......Page 663
Figure 835 Using the 74x163 as a modulo-11 counter with the counting sequence 5, 6, º, 15, 5, 6, º.......Page 664
Figure 837 A 74x163 used as an excess-3 decimal counter.......Page 665
Figure 839 General cascading connections for 74x163-based counters.......Page 666
Figure 840 Using 74x163s as a modulo-193 counter with the counting sequence 63, 64, º, 255, 63, .........Page 667
Figure 842 A modulo-8 binary counter and decoder.......Page 668
Figure 843 Timing diagram for a modulo-8 binary counter and decoder, showing decoding glitches.......Page 669
8.4.5 Counters in ABEL and PLDs......Page 670
Table 813 MInimized equations for the 4-bit binary counter in Table812.......Page 671
Table 814 VHDL program for a 74x163-like 4-bit binary counter.......Page 673
Table 815 VHDL architecture for counting in excess-3 order.......Page 674
Table 816 VHDL program for counter cell of Figure845.......Page 675
Table 817 VHDL program for an 8-bit 74x163-like synchronous serial counter.......Page 676
Figure 847 Structure of a serial-in, parallel-out shift register.......Page 677
Figure 849 Structure of a parallel-in, parallel-out shift register.......Page 678
Figure 850 Traditional logic symbols for MSI shift registers: (a) 74x164 8-bit serial-in, parall.........Page 679
Figure 851 Logic diagram for the 74x194 4-bit universal shift register, including pin numbers f.........Page 680
Table 819 Function table for a 74x299 8-bit universal shift register.......Page 681
Figure 853 Logic diagram for the 74x299 8-bit universal shift register, including pin numbers f.........Page 682
I Still Don’t Know......Page 683
The Nation’s Clock......Page 684
Figure 855 Timing diagram for parallel-to-serial conversion: (a) a complete frame; (b) one byte.........Page 685
Figure 856 Parallel-to-serial conversion using a parallel-in shift register.......Page 686
Figure 857 Serial-to-parallel conversion using a parallel-out shift register.......Page 687
Figure 858 Timing diagram for serial-to-parallel conversion.......Page 688
Figure 859 Simplest design for a four-bit, four-state ring counters with a single circulating 1.......Page 689
Figure 861 State diagram for a simple ring counter.......Page 690
Figure 863 State diagram for a self-correcting ring counter.......Page 691
*8.5.7 Johnson Counters......Page 692
Table 820 States of a 4-bit Johnson counter.......Page 693
The Self- Correction Circuit Is Itself Correct!......Page 694
Figure 868 General structure of a linear feedback shift-register counter.......Page 695
Table 821 Feedback equations for linear feedback shift-register counters.......Page 696
Table 822 State sequences for the 3-bit LFSR counter in Figure869.......Page 697
Figure 870 PLD realizations of a 74x194-like universal shift register with synchronous clear.......Page 698
Table 823 ABEL program for a 4-bit universal shift register.......Page 699
Table 824 ABEL program for a multi-function shift register.......Page 700
Table 825 Program for an 8-bit ring counter.......Page 701
Table 826 Program for a six-phase waveform generator.......Page 702
Table 827 (continued)Alternate program for the waveform generator.......Page 703
Reliable Reset......Page 704
Table 828 Additions to Table826 for a modified six-phase waveform generator.......Page 705
Table 829 ABEL program for a modified six-phase waveform generator.......Page 706
8.5.10 Shift Registers in VHDL......Page 707
Table 831 Function table for an extended-function 8-bit shift register.......Page 708
Table 832 VHDL program for an extended-function 8-bit shift register.......Page 709
Table 833 VHDL program for a six-phase waveform generator.......Page 710
Table 834 VHDL program for a modified six-phase waveform generator.......Page 711
Figure 874 General structure of the sequential-circuit version of an iterative circuit.......Page 712
Figure 876 Detailed serial comparator circuit.......Page 713
Figure 878 Serial binary adder circuit.......Page 714
8.7.1 Synchronous System Structure......Page 715
Figure 879 Synchronous system structure.......Page 716
Pipelined Mealy Outputs......Page 717
Figure 881 Registers and functions used by the shift-and-add multiplication algorithm.......Page 718
Figure 882 Data unit of an 8-bit shift-and-add binary multiplier.......Page 719
Figure 883 Control unit for an 8-bit shift-and-add binary multiplier.......Page 720
Figure 884 State diagram for the control state machine for a shift-and-add binary multiplier.......Page 721
Figure 885 Example of clock skew.......Page 722
Figure 886 Buffering the clock: (a) excessive clock skew; (b) controllable clock skew.......Page 723
Figure 888 Clock-signal routing to minimize skew.......Page 724
8.8.2 Gating the Clock......Page 725
Figure 890 An acceptable way to gate the clock: (a) circuit; (b) timing diagram.......Page 726
Figure 891 A single, simple synchronizer: (a) logic diagram; (b) timing.......Page 727
Figure 893 An asynchronous input driving two synchronizers through combinational logic.......Page 728
8.9 Synchronizer Failure and Metastability......Page 729
Figure 895 A failed attempt to build a metastable- proof S-R flip-flop.......Page 730
Figure 896 Recommended synchronizer design.......Page 731
Details, Details......Page 732
Understanding a and f......Page 733
Table 835 Metastability parameters for some common devices.  ......Page 734
Figure 899 Multiple-cycle synchronizer with deskewing.......Page 736
Figure 8100 Cascaded synchronizer.......Page 737
Figure 8101 Logic diagram for the 74AS4374 octal dual-rank D flip-flop.......Page 738
One Nibble at a Time......Page 739
Figure 8104 Byte holding register and control.......Page 740
Figure 8106 SCTRL circuit for generating SLOAD.......Page 741
Figure 8107 Timing for the SCTRL circuit in Figure8106.......Page 742
Figure 8108 Maximum-delay timing for SCTRL circuit.......Page 743
Figure 8109 Half-clock-period SCTRL circuit for generating SLOAD.......Page 746
Figure 8110 Synchronizer timing with slow (10 MHz) RCLK.......Page 747
Figure 8111 Synchronizer with edge-triggered SYNC detection.......Page 748
References......Page 749
Drill Problems......Page 751
Exercises......Page 752
Sequential-Circuit Design Examples......Page 760
9.1.1 Timing and Packaging of PLD-Based State Machines......Page 761
Figure 91 Structure and timing of a PLD used as a state machine.......Page 762
Figure 92 Splitting a state-machine design into three PLDs.......Page 763
9.1.2 A Few Simple Machines......Page 764
Resetting Bad Habits......Page 765
Finite-Memory Design......Page 766
Figure 93 General structure of a finite-memory machine.......Page 767
Figure 94 A single-PLD design for T-bird tail lights.......Page 768
9.1.4 The Guessing Game......Page 769
Table 95 ABEL program for the guessing-game machine.......Page 770
Table 97 ABEL definitions for the guessing-game machine with an output-coded state assignment.......Page 771
Table 98 Output coding for the guessing-game machine using “don’t cares.”......Page 772
9.1.5 Reinventing Traffic-Light Controllers......Page 773
9.2.1 A Few Simple Machines......Page 778
Table 913 VHDL program for state-machine example.......Page 779
Table 915 Using standard logic and constants to specify a state encoding.......Page 781
Table 916 Simplified state machine for VHDL example problem.......Page 783
Table 917 VHDL program for a ones-counting machine.......Page 784
Table 918 Alternative VHDL process for ones- counting machine.......Page 785
Table 919 VHDL program for finite-memory design of combination-lock state machine.......Page 786
9.2.2 T-Bird Tail Lights......Page 787
Idle Musings......Page 788
9.2.4 Reinventing Traffic-Light Controllers......Page 790
Exercises......Page 794