Definitive guide to Arm Cortex-M23 and Cortex-M33 processors

Front Cover
Definitive Guide to Arm® Cortex®-M23 and Cortex-M33 Processors
Copyright
Dedication
Contents
Preface
Contributing author: Paul Beckmann
Acknowledgments
Chapter 1: Introduction
	1.1. Microcontrollers and processors
	1.2. Classification of processors
	1.3. The Cortex-M23 and Cortex-M33 processors and the Armv8-M architecture
	1.4. Characteristics of the Cortex-M23 and Cortex-M33 processors
	1.5. Why have two different processors?
	1.6. Applications of the Cortex-M23 and Cortex-M33
	1.7. Technical features
	1.8. Comparison with previous generations of Cortex-M processors
	1.9. Advantages of the Cortex-M23 and Cortex-M33 processors
	1.10. Understanding microcontroller programming
	1.11. Further reading
		1.11.1. Product pages on developer.arm.com
		1.11.2. Documentation on developer.arm.com
		1.11.3. Community.arm.com
	References
Chapter 2: Getting started with Cortex-M programming
	2.1. Overview
		2.1.1. Development suites
		2.1.2. Development board
		2.1.3. Debug adaptor
		2.1.4. Resources
	2.2. Some basic concepts
		2.2.1. Reset
		2.2.2. Clocks
		2.2.3. Voltage level
		2.2.4. Inputs and outputs
		2.2.5. Introduction to embedded software program flows
			2.2.5.1. Polling method
			2.2.5.2. Interrupt driven method
			2.2.5.3. Combination of polling and interrupt-driven methods
			2.2.5.4. Handling concurrent processes
	2.3. Introduction to Arm Cortex-M programming
		2.3.1. C Programming-Data types
		2.3.2. Accessing peripherals in C
		2.3.3. What is inside a program image?
			2.3.3.1. Vector table
			2.3.3.2. Reset handler/startup code
			2.3.3.3. C startup code
			2.3.3.4. Application code
			2.3.3.5. C library code
			2.3.3.6. Other data
		2.3.4. Data in SRAM
		2.3.5. What happens when a microcontroller starts?
		2.3.6. Understanding your hardware platform
	2.4. Software development flow
	2.5. Cortex Microcontroller Software Interface Standard (CMSIS)
		2.5.1. Introduction of CMSIS
		2.5.2. What is standardized in the CMSIS-CORE?
		2.5.3. Using CMSIS-CORE
		2.5.4. Benefits of CMSIS
	2.6. Additional information on software development
	Reference
Chapter 3: Technical overview of the Cortex-M23 and Cortex-M33 processors
	3.1. Design objectives of Cortex-M23 and Cortex-M33 processors
	3.2. Block diagrams
		3.2.1. Cortex-M23
		3.2.2. Cortex-M33
	3.3. Processor
	3.4. Instruction set
	3.5. Memory map
	3.6. Bus interfaces
	3.7. Memory protection
	3.8. Interrupt and exception handling
	3.9. Low power features
	3.10. OS support features
	3.11. Floating-point unit
	3.12. Coprocessor interface and Arm Custom Instructions
	3.13. Debug and trace support
	3.14. Multicore system design support
	3.15. Key feature enhancements in Cortex-M23 and Cortex-M33 processors
		3.15.1. Comparison between Cortex-M0+ and Cortex-M23 processors
		3.15.2. Comparison between Cortex-M3/M4 and Cortex-M33 processors
	3.16. Compatibility with other Cortex-M processors
	3.17. Processor configuration options
	3.18. Introduction to TrustZone
		3.18.1. Overview of security requirements
		3.18.2. Evolution of security in embedded systems
		3.18.3. TrustZone for Armv8-M
	3.19. Why TrustZone enables better security?
	3.20. Firmware asset protection with eXecute-Only-Memory (XOM)
	Reference
Chapter 4: Architecture
	4.1. Introduction to the Armv8-M architecture
		4.1.1. Overview
		4.1.2. Background to the Armv8-M architecture
	4.2. Programmer\'s model
		4.2.1. Processor modes and states
		4.2.2. Registers
			4.2.2.1. Various types of registers
			4.2.2.2. Registers in the register bank
			4.2.2.3. Special registers
				Program Status Register (PSR)
				Interrupt masking registers
				CONTROL register
				Stack limit registers
			4.2.2.4. Floating-point registers in Cortex-M33
		4.2.3. Behaviors of the APSR (ALU status flags)
			4.2.3.1. Integer status flags
			4.2.3.2. Q status flag
			4.2.3.3. GE bits
		4.2.4. Impact of TrustZone on the programmer\'s model
	4.3. Memory system
		4.3.1. Memory map
		4.3.2. Partitioning of address spaces within TrustZone
		4.3.3. System control space (SCS) and system control block (SCB)
		4.3.4. Stack memory
		4.3.5. Setting up and accessing of stack pointers and stack limit registers
		4.3.6. Memory protection unit (MPU)
	4.4. Exceptions and Interrupts
		4.4.1. What are exceptions
		4.4.2. TrustZone and exceptions
		4.4.3. Nested Vectored Interrupt Controller (NVIC)
			4.4.3.1. Flexible exception and interrupt management
			4.4.3.2. Nested exception/interrupt support
			4.4.3.3. Vectored exception/interrupt entry
			4.4.3.4. Interrupt masking
		4.4.4. Interrupt management with CMSIS-CORE
		4.4.5. Vector tables
		4.4.6. Fault handling
	4.5. Debug
	4.6. Reset and reset sequence
	4.7. Other related architecture information
	References
Chapter 5: Instruction set
	5.1. Background
		5.1.1. About this chapter
		5.1.2. Background to the Instruction set in Arm Cortex-M processors
	5.2. Instruction set features in various Cortex-M processors
	5.3. Understanding the assembly language syntax
	5.4. Use of a suffix in an instruction
	5.5. Unified Assembly Language (UAL)
	5.6. Instruction set-Moving data within the processors
		5.6.1. Overview
		5.6.2. Moving data between registers
		5.6.3. Immediate data generation
		5.6.4. Special register access instructions
		5.6.5. Floating point register access
		5.6.6. Floating point immediate data generation
		5.6.7. Moving data between a register and a coprocessor register
	5.7. Instruction set-Memory access
		5.7.1. Overview
		5.7.2. Single memory access
		5.7.3. SP relative load/stores
		5.7.4. Preindexed and postindex addressing modes
		5.7.5. Optional shift in register offset (Barrel shifter)
		5.7.6. Literal data read
		5.7.7. Multiple load/store
		5.7.8. PUSH/POP
		5.7.9. Unprivileged access instructions
		5.7.10. FPU memory access instructions
		5.7.11. Exclusive access
		5.7.12. Load acquire-store release
	5.8. Instruction set-Arithmetic operations
	5.9. Instruction set-Logic operations
	5.10. Instruction set-Shift and rotate operations
	5.11. Instruction set-Data conversions (extend and reverse ordering)
	5.12. Instruction set-Bit field processing
	5.13. Instruction set-Saturation operations
	5.14. Instruction set-Program flow control
		5.14.1. Overview
		5.14.2. Branch
		5.14.3. Function call
		5.14.4. Conditional branch
		5.14.5. Compare and branches (CBZ, CBNZ)
		5.14.6. Conditional execution (IF-THEN instruction block)
		5.14.7. Table branches (TBB and TBH)
	5.15. Instruction set-DSP extension
		5.15.1. Overview
		5.15.2. SIMD concept
		5.15.3. SIMD and saturating arithmetic instructions
		5.15.4. Multiply and MAC instructions
		5.15.5. Packing and unpacking instructions
	5.16. Instruction set-Floating point support instructions
		5.16.1. Overview of floating-point support in Armv8-M processors
		5.16.2. Enabling the FPU
		5.16.3. Floating point instructions
	5.17. Instruction set-Exception-related instructions
	5.18. Instruction set-Sleep mode-related instructions
	5.19. Instruction set-Memory barrier instructions
	5.20. Instruction set-TrustZone support instructions
	5.21. Instruction set-Coprocessor and Arm custom instructions support
	5.22. Instruction set-Other functions
	5.23. Accessing special registers with the CMSIS-CORE
	References
Chapter 6: Memory system
	6.1. Overview of the memory system
		6.1.1. What is in the memory system?
		6.1.2. Memory system features
		6.1.3. Key changes for the Cortex-M23/M33 when compared to the previous Cortex-M processors
	6.2. Memory map
	6.3. Memory types and memory attributes
		6.3.1. Memory type classifications
		6.3.2. Memory attributes overview
		6.3.3. Memory attributes of the default memory map
	6.4. Access permission management
		6.4.1. Overview of access permission management
		6.4.2. Access control mechanisms
		6.4.3. Differences between the SAU/IDAU and the MPU
		6.4.4. Default access permission
	6.5. Memory endianness
	6.6. Data alignment and unaligned data access support
	6.7. Exclusive access support
	6.8. Memory ordering and memory barrier instructions
	6.9. Bus wait state and error support
	6.10. Single-cycle I/O port-Cortex-M23 only
	6.11. Memory systems in microcontrollers
		6.11.1. Memory requirements
		6.11.2. Bus system designs
		6.11.3. Security management
	6.12. Software considerations
		6.12.1. Bus level power management
		6.12.2. TrustZone security
		6.12.3. Use of multiple load and store instructions
	References
Chapter 7: TrustZone support in the memory system
	7.1. Overview
		7.1.1. About this chapter
		7.1.2. Memory security attributes
	7.2. SAU and IDAU
	7.3. Banked and nonbanked registers
		7.3.1. Overview
		7.3.2. System Control Space (SCS) NS alias
	7.4. Test Target (TT) instructions and region ID numbers
		7.4.1. Why are the TT instructions needed?
		7.4.2. The TT instructions
		7.4.3. Region ID numbers
	7.5. Memory protection controller and peripheral protection controller
	7.6. Security aware peripherals
	References
Chapter 8: Exceptions and interrupts-Architecture overview
	8.1. Overview of exceptions and interrupts
		8.1.1. The need for exceptions and interrupts
		8.1.2. Basic concepts of peripheral interrupt operations
		8.1.3. Introduction to the NVIC
	8.2. Exception types
	8.3. Overview of interrupts and exceptions management
	8.4. Exception sequence introduction
		8.4.1. Overview
		8.4.2. Acceptance of exception request
		8.4.3. Exception entry sequence
		8.4.4. Exception handler execution
		8.4.5. Exception return sequence
	8.5. Definitions of exception priority levels
		8.5.1. Overview of exception and interrupt priority levels
		8.5.2. Priority grouping in Armv8-M Mainline
		8.5.3. Prioritization of Secure exceptions and interrupts
		8.5.4. Banking of interrupt mask registers
	8.6. Vector table and vector table offset register (VTOR)
	8.7. Interrupt input and pending behaviors
	8.8. Target states of exceptions and interrupts in TrustZone systems
	8.9. Stack frames
		8.9.1. Stacking and unstacking overview
		8.9.2. Interface of C functions
		8.9.3. Exception handler in C
		8.9.4. Stack frame formats
		8.9.5. Which stack pointer is used for stacking and unstacking?
	8.10. EXC_RETURN
	8.11. Classification of synchronous and asynchronous exceptions
	References
Chapter 9: Management of exceptions and interrupts
	9.1. Overview of exception and interrupt management
		9.1.1. Access to exception management functions
		9.1.2. Basic interrupt management in the CMSIS-CORE
		9.1.3. Additional interrupt management functions in CMSIS-CORE
		9.1.4. System exception management
	9.2. Details of the NVIC registers for interrupt management
		9.2.1. Summary
		9.2.2. Interrupt Enable Registers
		9.2.3. Interrupt Set Pending and Clear Pending Registers
		9.2.4. Active status
		9.2.5. Interrupt Target Non-secure Register(s)
		9.2.6. Priority level
		9.2.7. Software Trigger Interrupt Register (Armv8-M mainline only)
		9.2.8. Interrupt Controller Type Register
		9.2.9. NVIC feature enhancements
	9.3. Details of SCB registers for system exception management
		9.3.1. Summary
		9.3.2. Interrupt Control and State Register (SCB->ICSR)
		9.3.3. System Handler Priority Registers (SCB->SHP[n])
		9.3.4. Application Interrupt and Reset Control Register (SCB->AIRCR)
		9.3.5. System Handler Control and State Register (SCB->SHCSR)
	9.4. Details of special registers for exception or interrupt masking
		9.4.1. Overview of interrupt masking registers
		9.4.2. PRIMASK
		9.4.3. FAULTMASK
		9.4.4. BASEPRI
	9.5. Vector table definition in programming
		9.5.1. Vector table in startup code
		9.5.2. Vector table relocation
	9.6. Interrupt latency and exception handling optimizations
		9.6.1. What is interrupt latency
		9.6.2. Interrupts during multiple-cycle instructions
		9.6.3. Tail chaining
		9.6.4. Late arrival
		9.6.5. Pop preemption
		9.6.6. Lazy stacking
	9.7. Tips and hints
	References
Chapter 10: Low power and system control features
	10.1. The quest for low power
		10.1.1. Why low power is important?
		10.1.2. What does low power mean? And how to measure it?
	10.2. Low power features in the Cortex-M23 and Cortex-M33 processors
		10.2.1. Low power characteristics
		10.2.2. Sleep modes
		10.2.3. System Control Register (SCB->SCR)
		10.2.4. Entering sleep mode
		10.2.5. Sleep-on-Exit feature
		10.2.6. Send Event On Pend (SEVONPEND)
		10.2.7. Sleep extension/wakeup delay
		10.2.8. Wakeup Interrupt Controller (WIC)
		10.2.9. Event communication interface
		10.2.10. Effect of TrustZone on sleep mode support
	10.3. More on WFI, WFE, and SEV instructions
		10.3.1. Using WFI, WFE, and SEV instructions in programming
		10.3.2. When to use WFI
		10.3.3. When to use WFE
		10.3.4. Wake up conditions
	10.4. Developing low power applications
		10.4.1. Getting started
		10.4.2. Reducing the active power
			10.4.2.1. Choose the right microcontroller device
			10.4.2.2. Running at the right clock frequency
			10.4.2.3. Select the right clock source
			10.4.2.4. Turn off unused clock signals
			10.4.2.5. Utilized clock system features
			10.4.2.6. Power supply design
			10.4.2.7. Modify the idle thread of RTOS
			10.4.2.8. Modify the clock control of RTOS
			10.4.2.9. Running program from SRAM
			10.4.2.10. Choosing the right I/O port configuration
		10.4.3. Reduction of active cycles
			10.4.3.1. Utilizing the sleep modes
			10.4.3.2. Reducing the run time
		10.4.4. Sleep mode current reduction
			10.4.4.1. Using the right sleep mode
			10.4.4.2. Utilizing the power control features
	10.5. System Control Block (SCB) and system control features
		10.5.1. Registers in the System Control Block (SCB)
		10.5.2. CPU ID base register
		10.5.3. AIRCR-Self-reset generation (SYSRESETREQ)
		10.5.4. AIRCR-Clearing all interrupt states (VECTCLRACTIVE)
		10.5.5. CCR-Configuration and Control Register (SCB->CCR, 0xE000ED14)
			10.5.5.1. CCR overview
			10.5.5.2. CCR-STKOFHFNMIGN bit
			10.5.5.3. CCR-BFHFNMIGN bit
			10.5.5.4. CCR-DIV_0_TRP bit
			10.5.5.5. CCR-UNALIGN_TRP bit
			10.5.5.6. CCR-USERSETMPEND bit
	10.6. Auxiliary Control Register
		10.6.1. Overview of the Auxiliary Control Register
		10.6.2. Auxiliary Control Register for the Cortex-M23 processor
		10.6.3. Auxiliary Control Register for the Cortex-M33 processor
	10.7. Other registers in the System Control Block
Chapter 11: OS support features
	11.1. Overview of the OS support features
	11.2. SysTick timer
		11.2.1. Purpose of the SysTick timer
		11.2.2. SysTick timer operations
		11.2.3. Using the SysTick timer
			11.2.3.1. Using the SysTick timer for RTOS
			11.2.3.2. Using the SysTick timer with CMSIS-CORE
			11.2.3.3. Using SysTick timer without using SysTick_Config()
			11.2.3.4. Using the SysTick timer for timing measurement
		11.2.4. TrustZone and SysTick timer
		11.2.5. Other considerations
	11.3. Banked stack pointers
		11.3.1. Benefits of banked stack pointers
		11.3.2. Operations of banked stack pointers
		11.3.3. Banked stack pointers in bare metal systems
	11.4. Stack limit checking
		11.4.1. Overview
		11.4.2. Access to the stack limit registers
		11.4.3. Protection of the Main Stack Pointer(s)
	11.5. SVCall and PendSV exceptions
		11.5.1. Overview of SVCall and PendSV
		11.5.2. SVCall
		11.5.3. PendSV
	11.6. Unprivileged execution level and the Memory Protection Unit (MPU)
	11.7. Exclusive access
	11.8. How should an RTOS run in a TrustZone environment?
	11.9. Concepts of RTOS operations in Cortex-M processors
		11.9.1. Starting a simple OS
		11.9.2. Context switching
		11.9.3. Context switching in action
	References
Chapter 12: Memory Protection Unit (MPU)
	12.1. Overview of the MPU
		12.1.1. Introduction
		12.1.2. MPU operation concepts
		12.1.3. MPU support in Arm Cortex-M23 and Cortex-M33 processors
		12.1.4. Architectural requirements when using the MPU
	12.2. MPU registers
		12.2.1. Summary of the MPU registers
		12.2.2. MPU Type register
		12.2.3. MPU Control register
		12.2.4. MPU Region Number Register
		12.2.5. MPU Region Base Address Register
		12.2.6. MPU Region Limit Address Register
		12.2.7. MPU RBAR and RLAR alias registers
		12.2.8. MPU Attribute Indirection Register 0 and 1
	12.3. Configuration of the MPU
		12.3.1. Overview of the MPU\'s configuration steps
		12.3.2. Defining the memory attributes for MAIR0 and MAIR1
		12.3.3. MPU programming
			12.3.3.1. Overview
			12.3.3.2. Disable MPU
			12.3.3.3. Program MAIR0 and MAIR1
			12.3.3.4. Region Base Address and Limit Address registers
			12.3.3.5. Enable the MPU
	12.4. TrustZone and MPU
	12.5. Key differences between the MPU in Armv8-M architecture and the architecture of the previous generations
	References
Chapter 13: Fault exceptions and fault handling
	13.1. Overview
	13.2. Cause of faults
		13.2.1. Memory management (MemManage) fault causes
		13.2.2. Bus faults
		13.2.3. Usage Faults
		13.2.4. SecureFault
		13.2.5. HardFault
		13.2.6. Faults triggered by exception handling
	13.3. Enabling fault exceptions
	13.4. Fault handler designs considerations
		13.4.1. Stack pointer validation check
		13.4.2. Making sure the SVC is not accidentally used in the HardFault and NMI handlers
		13.4.3. Triggering self-reset or halting
		13.4.4. Partitioning of fault handler
		13.4.5. Using the Fault Mask in a configurable fault handler
	13.5. Fault status and other information
		13.5.1. Overview of fault status registers and fault address registers
		13.5.2. MemManage Fault Status Register (MMFSR)
		13.5.3. BusFault Status Register (BFSR)
		13.5.4. Usage Fault Status Register (UFSR)
		13.5.5. Secure Fault Status Register (SFSR)
		13.5.6. HardFault Status Register (HFSR)
		13.5.7. Debug Fault Status Register (DFSR)
		13.5.8. Auxiliary Fault Status Register (AFSR)
		13.5.9. Fault address registers (BFAR, MMFAR, and SFAR)
	13.6. Lockup
		13.6.1. What is Lockup?
		13.6.2. Avoiding Lockup
	13.7. Analysis of fault events
		13.7.1. Overview
		13.7.2. Key differences between the fault handling in Armv8-M architecture and the architecture of previous generations
	13.8. Stack trace
	13.9. Fault handler to extract stack frame and display fault status
	Reference
Chapter 14: The Floating-Point Unit (FPU) in the Cortex-M33 processor
	14.1. Floating-point data
		14.1.1. Introduction
		14.1.2. Single precision floating-point numbers
		14.1.3. Half precision floating-point numbers
		14.1.4. Double precision floating-point numbers
		14.1.5. Floating-point support in Arm Cortex-M processors
	14.2. Cortex-M33 Floating-point Unit (FPU)
		14.2.1. FPU overview
		14.2.2. Floating-point registers overview
		14.2.3. CPACR register
		14.2.4. NSACR register
		14.2.5. Floating-point register bank
		14.2.6. Floating-point Status and Control Register (FPSCR)
		14.2.7. Floating-Point Context Control Register (FPU->FPCCR)
		14.2.8. Floating-Point Context Address Register (FPU->FPCAR)
		14.2.9. Floating-Point Default Status Control Register (FPU->FPDSCR)
		14.2.10. Media and FP Feature Registers (FPU->MVFR0 to FPU->MVFR2)
	14.3. Key differences between the FPUs of the Cortex-M33 FPU and the Cortex-M4
	14.4. Lazy stacking in details
		14.4.1. Key elements of the Lazy Stacking feature
		14.4.2. Scenario #1: no floating-point context in an interrupted task
		14.4.3. Scenario #2: floating-point context in an interrupted task but not in the ISR
		14.4.4. Scenario #3: floating-point context in an interrupted task and in the ISR
		14.4.5. Scenario #4: Nested Interrupt with FP context in the second handler
		14.4.6. Scenario #5: Nested interrupt with FP context in the both handlers
		14.4.7. Interrupt during a lazy stacking operation
		14.4.8. Interrupt of floating-point instructions
	14.5. Using the FPU
		14.5.1. Floating-point support in the CMSIS-CORE
		14.5.2. Floating-point programming in C language
		14.5.3. Compiler command line options
		14.5.4. ABI options: Hard-vfp and soft-vfp
		14.5.5. Special FPU modes
		14.5.6. Power down the FPU
	14.6. Floating-point exceptions
	14.7. Hints and tips
		14.7.1. Runtime libraries for microcontrollers
		14.7.2. Debug operation
	References
Chapter 15: Coprocessor interface and Arm Custom Instructions
	15.1. Overview
		15.1.1. Introduction
		15.1.2. The purpose of coprocessors and Arm custom instructions
		15.1.3. Coprocessor interface and Arm Custom Instructions features
		15.1.4. Comparing the coprocessor and the Arm Custom Instructions with memory mapped hardware accelerators
		15.1.5. Why these are called coprocessors?
	15.2. Overview of the architecture
	15.3. Accessing coprocessor instructions via intrinsic functions in C
	15.4. Accessing Arm Custom Instructions via the intrinsic functions in C
	15.5. Software steps to take when enabling the coprocessor and the Arm Custom Instructions
	15.6. Coprocessor power control
	15.7. Hints and tips
	References
Chapter 16: Introduction to the debug and trace features
	16.1. Introduction
		16.1.1. Overview
		16.1.2. CoreSight architecture
		16.1.3. Classification of debug and trace features
		16.1.4. Debug and trace features summary
	16.2. Debug architecture details
		16.2.1. Debug connection
		16.2.2. Trace connection-Real time trace
		16.2.3. Trace buffer
		16.2.4. Debug modes
		16.2.5. Debug events
		16.2.6. Using the breakpoint instruction
		16.2.7. Debug authentication and TrustZone
		16.2.8. CoreSight discovery: The identification of debug components
	16.3. An introduction to debug components
		16.3.1. Overview
		16.3.2. Debug support registers in the processor core
		16.3.3. Breakpoint unit
		16.3.4. Data Watchpoint and Trace Unit (DWT)
		16.3.5. Instrumentation Trace Macrocell (ITM)
			16.3.5.1. Overview
			16.3.5.2. Programmer\'s model
			16.3.5.3. Hardware trace with ITM and DWT
			16.3.5.4. ITM timestamp
		16.3.6. Embedded Trace Macrocell (ETM)
		16.3.7. Micro Trace Buffer (MTB)
		16.3.8. Trace Port Interface Unit (TPIU)
		16.3.9. Cross Trigger Interface (CTI)
	16.4. Starting a debug session
	16.5. Flash memory programming support
	16.6. Software design considerations
	References
Chapter 17: Software development
	17.1. Introduction
		17.1.1. Software development overview
		17.1.2. Inside a typical Cortex-M software project
	17.2. Getting started with the Keil Microcontroller Development Kit (MDK)
		17.2.1. Overview of Keil MDK features
		17.2.2. Typical program compilation flow
		17.2.3. Creating a new project from scratch
		17.2.4. Understanding the project options
			17.2.4.1. Overview
			17.2.4.2. Device options
			17.2.4.3. Target options
			17.2.4.4. Output options
			17.2.4.5. Listing options
			17.2.4.6. User options
			17.2.4.7. C/C++ options
			17.2.4.8. Assembler options
			17.2.4.9. Linker options
			17.2.4.10. Debug options
			17.2.4.11. Utilities options
		17.2.5. Defining stack and heap sizes in a Keil MDK project
			17.2.5.1. Determining the required stack and heap sizes
			17.2.5.2. Projects with assembly startup codes
			17.2.5.3. Projects with C startup codes
		17.2.6. Using the IDE and the debugger
		17.2.7. Printf with UART
		17.2.8. Printf with ITM
		17.2.9. Using a Real-Time OS-RTX
		17.2.10. Inline assembly
	17.3. Procedure Call Standard for the Arm Architecture
	17.4. Software scenarios
		17.4.1. A recap of the software development scenarios
		17.4.2. Scenario #1-The Armv8-M system does not implement TrustZone
		17.4.3. Scenario #2-Development of Non-secure software where the Secure world is not used
		17.4.4. Scenario #3-Development of Non-secure software when the Secure world is used
		17.4.5. Scenario #5-Development of Secure software where the Non-secure world is not used
	References
Chapter 18: Secure software development
	18.1. Overview of Secure software development
		18.1.1. Introduction
		18.1.2. The separation of Secure and Non-secure in software projects
		18.1.3. Cortex-M Security Extension (CMSE)
		18.1.4. Trusted Firmware-M
		18.1.5. Development platform considerations
	18.2. TrustZone technical details
		18.2.1. Processor state
		18.2.2. Memory separation
		18.2.3. SAU programmer\'s model
			18.2.3.1. Summary of SAU registers and concepts
			18.2.3.2. SAU Control Register
			18.2.3.3. SAU Type Register
			18.2.3.4. SAU Region Number Register
			18.2.3.5. SAU Region Base Address Register
			18.2.3.6. SAU Region Limit Address Register
			18.2.3.7. Secure Fault Status Register (SFSR) and Secure Fault Address Register (SFAR)
		18.2.4. Non-secure software calling a Secure API
		18.2.5. Secure code calling a Non-secure function
		18.2.6. Additional information for the BXNS and BLXNS instructions
		18.2.7. Security state transition-Privileged level change
		18.2.8. Security state transitions and their relationship with exception priority levels
		18.2.9. Other TrustZone instructions
	18.3. Secure software development
		18.3.1. Overview of Secure software development
		18.3.2. Security setup
		18.3.3. Initial switching to the Non-secure world
		18.3.4. Creating a simple Secure API
		18.3.5. Calling a Non-secure function
		18.3.6. Pointer checking
		18.3.7. Other CMSE features
		18.3.8. Passing parameters across security domains
		18.3.9. Software environments when TrustZone is not used
		18.3.10. Fault Handler
	18.4. Creating a Secure project in Keil MDK
		18.4.1. Creating a Secure project
		18.4.2. Creating a Non-secure project
		18.4.3. Creating a multiproject workspace
	18.5. CMSE support in other toolchains
		18.5.1. GNU C compiler (GCC)
		18.5.2. IAR
	18.6. Secure software design considerations
		18.6.1. Initial branching to the Non-secure world
		18.6.2. Non-secure callable (NSC)
			18.6.2.1. NSC region definition matching
			18.6.2.2. NSC region in SRAM
		18.6.3. Memory partitioning
			18.6.3.1. MPC and PPC behavior
			18.6.3.2. Dynamic switching of the security attribute of an SRAM page
			18.6.3.3. Dynamic switching of a peripheral\'s security attribute
		18.6.4. Input data and pointer validations
			18.6.4.1. Validation of input data in the Non-secure memory
			18.6.4.2. Always check a pointer before using it
			18.6.4.3. The danger of ``printf´´ in a Secure API
			18.6.4.4. Using the CMSE pointer check functions
		18.6.5. Peripheral driver
			18.6.5.1. Definition of peripheral registers
			18.6.5.2. Peripheral driver code
			18.6.5.3. Peripheral interrupts
		18.6.6. Other general recommendations
			18.6.6.1. Parameter passing
			18.6.6.2. Defining the stack, the heap, and the data RAM with the XN (eXecute Never) attribute
			18.6.6.3. Stack limit for the main stack
			18.6.6.4. Preventing a stack underflow attack
			18.6.6.5. Check all Secure entry points to prevent unintentional entry points
			18.6.6.6. Restricting a Secure library to unprivileged execution level
			18.6.6.7. Reentrancy of Secure functions
			18.6.6.8. The Secure handler must seal the Secure main stack when switching an exception handler to unprivileged execution
			18.6.6.9. Secure world not used
			18.6.6.10. PSA certification
	References
Chapter 19: Digital signal processing on the cortex-M33 processor
	19.1. DSP on a microcontroller?
	19.2. Why use a Cortex-M processor for a DSP application?
	19.3. Dot product example
	19.4. Getting more performance by utilizing the SIMD instructions
	19.5. Dealing with overflows
	19.6. Introduction to data types for signal processing
		19.6.1. Why we need the fixed-point data format
		19.6.2. Fractional arithmetic
		19.6.3. SIMD data
	19.7. Cortex-M33 DSP instructions
		19.7.1. Load and store instructions
		19.7.2. Arithmetic instructions
			19.7.2.1. 32-bit integer instructions
				ADD-32-bit addition
				SUB-32-bit subtraction
				SMULL-Long signed multiply
				SMLAL-Long signed multiply accumulate
				SSAT-Signed saturation
				SMMUL-32-bit multiply returning 32-most-significant-bits
				SMMLA-32-bit multiply with 32-most-significant-bit accumulate
				QADD-32-bit saturating addition
				SDIV-32-bit division
			19.7.2.2. 16-bit integer instructions
				SADD16-Dual 16-bit addition
				QADD16-Dual 16-bit saturating addition
				SSAT16-Dual 16-bit saturate
				SMLABB-Q setting 16-bit signed multiply with 32-bit accumulate, bottom by bottom
				SMLAD-Q setting dual 16-bit signed multiply with single 32-bit accumulator
				SMLALBB-16-bit signed multiply with 64-bit accumulate, bottom by bottom
				SMLALD-Dual 16-bit signed multiply with single 64-bit accumulator
			19.7.2.3. 8-bit integer instructions
				SADD8-Quad 8-bit addition
				QADD8-Quad 8-bit saturating addition
			19.7.2.4. Floating-point instructions
				VABS.F32-Floating-point absolute value
				VADD.F32-Floating-point addition
				VDIV.F32-Floating-point division
				VMUL.F32-Floating-point multiplication
				VMLA.F32-Floating-point multiply accumulate
				VFMA.F32-Fused floating-point multiply accumulate
				VNEG.F32-Floating-point negation
				VSQRT.F32-Floating-point square root
				VSUB.F32-Floating-point subtraction
		19.7.3. General Cortex-M33 optimization strategies
			19.7.3.1. Scheduling of load and store instructions
			19.7.3.2. Examine the intermediate assembly code
			19.7.3.3. Enable optimization
			19.7.3.4. Performance considerations in MAC instructions
			19.7.3.5. Loop unrolling
			19.7.3.6. Focus on the inner loop
			19.7.3.7. Inline functions
			19.7.3.8. Count registers
			19.7.3.9. Use the right amount of precision
		19.7.4. Instruction limitations
	19.8. Writing optimized DSP code for the Cortex-M33 processor
		19.8.1. Biquad filter
		19.8.2. Fast Fourier Transform
		19.8.3. FIR filter
	References
Chapter 20: Using the Arm CMSIS-DSP library
	20.1. Overview of the library
	20.2. Function naming convention
	20.3. Getting help
	20.4. Example 1-DTMF demodulation
		20.4.1. Generating the sine wave
		20.4.2. Decoding using a FIR filter
		20.4.3. Decoding using an FFT
		20.4.4. Decoding using a Biquad filter
		20.4.5. Example of DTMF code
	20.5. Example 2-Least squares motion tracking
		20.5.1. Example of least squares code
	20.6. Example 3-Real-time filter design
		20.6.1. Overview of filter design
		20.6.2. Creating a real-time filter: A bare metal project example
		20.6.3. Filter processing in a low priority handler
		20.6.4. Use of an RTOS for handling filter processing
		20.6.5. Stereo audio biquad filter
		20.6.6. Alternative buffer arrangement
	20.7. How to determine the implemented instruction set features in a Cortex-M33 based system
	References
Chapter 21: Advanced topics
	21.1. Further information on stack memory protection
		21.1.1. Determining the stack memory usage
		21.1.2. Detecting stack overflow
	21.2. Semaphores, load-acquire and store-release instructions
	21.3. Unprivileged interrupt handler
	21.4. Re-entrant interrupt handler
	21.5. Software optimization topics
		21.5.1. Complex decision trees and conditional branches
		21.5.2. Complex decision tree
		21.5.3. Bit data handling in C/C++
		21.5.4. Other performance considerations
		21.5.5. Optimizations at assembly language level
	Reference
Chapter 22: Introduction to IoT security and the PSA Certified framework
	22.1. From processor architecture to IoT security
	22.2. Introduction of PSA Certified
		22.2.1. Overview of the security principles
		22.2.2. How to get there?
			22.2.2.1. The four pillars of PSA Certified
			22.2.2.2. Stage 1-Analyze
			22.2.2.3. Stage 2-Architect
			22.2.2.4. Stage 3-Implement
			22.2.2.5. Stage 4-Certify
		22.2.3. PSA Certified security evaluation levels
			22.2.3.1. Overview
			22.2.3.2. PSA Certified level 1
			22.2.3.3. PSA Certified level 2
			22.2.3.4. PSA Certified level 3
		22.2.4. PSA Functional API Certification
		22.2.5. Why PSA is important?
	22.3. The Trusted Firmware-M (TF-M) project
		22.3.1. About the TF-M project
		22.3.2. Software execution environment using TF-M
		22.3.3. PSA Functional APIs
		22.3.4. PSA interprocess communication
	22.4. Additional information
		22.4.1. Getting started
		22.4.2. Design considerations
	References
Index
Back Cover