Computer Organization and Architecture Designing for Performance

Cover......Page 1
Title Page......Page 4
Copyright Page......Page 5
ACKNOWLEDGMENTS......Page 23
Contents......Page 8
Foreword......Page 14
Preface......Page 16
About the Author......Page 24
Chapter 1 Basic Concepts and Computer Evolution......Page 26
1.1 Organization and Architecture......Page 27
1.2 Structure and Function......Page 28
1.3 A Brief History of Computers......Page 36
1.4 The Evolution of the Intel x86 Architecture......Page 52
1.5 Embedded Systems......Page 54
1.6 Arm Architecture......Page 58
1.7 Cloud Computing......Page 64
1.8 Key Terms, Review Questions, and Problems......Page 67
Chapter 2 Performance Issues......Page 70
2.1 Designing for Performance......Page 71
2.2 Multicore, Mics, and GPGPUs......Page 77
2.3 Two Laws that Provide Insight: Ahmdahl’s Law and Little’s Law......Page 78
2.4 Basic Measures of Computer Performance......Page 81
2.5 Calculating the Mean......Page 84
2.6 Benchmarks and Spec......Page 92
2.7 Key Terms, Review Questions, and Problems......Page 99
Chapter 3 A Top-Level View of Computer Function and Interconnection......Page 105
3.1 Computer Components......Page 106
3.2 Computer Function......Page 108
3.3 Interconnection Structures......Page 124
3.4 Bus Interconnection......Page 125
3.5 Point-to-Point Interconnect......Page 127
3.6 PCI Express......Page 132
3.7 Key Terms, Review Questions, and Problems......Page 141
Chapter 4 Cache Memory......Page 145
4.1 Computer Memory System Overview......Page 146
4.2 Cache Memory Principles......Page 153
4.3 Elements of Cache Design......Page 156
4.4 Pentium 4 Cache Organization......Page 174
4.5 Key Terms, Review Questions, and Problems......Page 177
Appendix 4A Performance Characteristics of Two-Level Memories......Page 182
Chapter 5 Internal Memory......Page 190
5.1 Semiconductor Main Memory......Page 191
5.2 Error Correction......Page 199
5.3 DDR DRAM......Page 205
5.4 Flash Memory......Page 210
5.5 Newer Nonvolatile Solid-State Memory Technologies......Page 212
5.6 Key Terms, Review Questions, and Problems......Page 215
Chapter 6 External Memory......Page 219
6.1 Magnetic Disk......Page 220
6.2 RAID......Page 229
6.3 Solid State Drives......Page 237
6.4 Optical Memory......Page 242
6.5 Magnetic Tape......Page 247
6.6 Key Terms, Review Questions, and Problems......Page 249
Chapter 7 Input/Output......Page 253
7.1 External Devices......Page 255
7.2 I/O Modules......Page 257
7.3 Programmed I/O......Page 260
7.4 Interrupt- Driven I/O......Page 264
7.5 Direct Memory Access......Page 273
7.6 Direct Cache Access......Page 279
7.7 I/O Channels and Processors......Page 286
7.8 External Interconnection Standards......Page 288
7.9 IBM zEnterprise EC12 I/O Structure......Page 291
7.10 Key Terms, Review Questions, and Problems......Page 295
Chapter 8 Operating System Support......Page 300
8.1 Operating System Overview......Page 301
8.2 Scheduling......Page 312
8.3 Memory Management......Page 318
8.4 Intel x86 Memory Management......Page 329
8.5 Arm Memory Management......Page 334
8.6 Key Terms, Review Questions, and Problems......Page 339
Chapter 9 Number Systems......Page 343
9.1 The Decimal System......Page 344
9.2 Positional Number Systems......Page 345
9.4 Converting Between Binary and Decimal......Page 346
9.5 Hexadecimal Notation......Page 349
9.6 Key Terms and Problems......Page 351
Chapter 10 Computer Arithmetic......Page 353
10.1 The Arithmetic and Logic Unit......Page 354
10.2 Integer Representation......Page 355
10.3 Integer Arithmetic......Page 360
10.4 Floating-Point Representation......Page 375
10.5 Floating-Point Arithmetic......Page 383
10.6 Key Terms, Review Questions, and Problems......Page 392
Chapter 11 Digital Logic......Page 397
11.1 Boolean Algebra......Page 398
11.2 Gates......Page 401
11.3 Combinational Circuits......Page 403
11.4 Sequential Circuits......Page 421
11.5 Programmable Logic Devices......Page 430
11.6 Key Terms and Problems......Page 434
Chapter 12 Instruction Sets: Characteristics and Functions......Page 437
12.1 Machine Instruction Characteristics......Page 438
12.2 Types of Operands......Page 445
12.3 Intel x86 and ARM Data Types......Page 447
12.4 Types of Operations......Page 450
12.5 Intel x86 and ARM Operation Types......Page 463
12.6 Key Terms, Review Questions, and Problems......Page 471
Appendix 12A Little-, Big-, and Bi- Endian......Page 477
Chapter 13 Instruction Sets: Addressing Modes and Formats......Page 481
13.1 Addressing Modes......Page 482
13.2 x86 and ARM Addressing Modes......Page 488
13.3 Instruction Formats 469......Page 494
13.4 x86 and ARM Instruction Formats......Page 502
13.5 Assembly Language......Page 507
13.6 Key Terms, Review Questions, and Problems......Page 509
Chapter 14 Processor Structure and Function......Page 513
14.1 Processor Organization......Page 514
14.2 Register Organization......Page 516
14.3 Instruction Cycle......Page 521
14.4 Instruction Pipelining......Page 525
14.5 The x86 Processor Family......Page 542
14.6 The ARM Processor......Page 549
14.7 Key Terms, Review Questions, and Problems......Page 555
Chapter 15 Reduced Instruction Set Computers......Page 560
15.1 Instruction Execution Characteristics......Page 562
15.2 The Use of a Large Register File......Page 567
15.3 Compiler-Based Register Optimization......Page 572
15.4 Reduced Instruction Set Architecture......Page 574
15.5 RISC Pipelining......Page 580
15.6 MIPS R4000......Page 584
15.7 SPARC......Page 590
15.8 RISC versus CISC Controversy......Page 595
15.9 Key Terms, Review Questions, and Problems......Page 596
Chapter 16 Instruction-Level Parallelism and Superscalar Processors......Page 600
16.1 Overview......Page 601
16.2 Design Issues......Page 606
16.3 Intel Core Microarchitecture......Page 616
16.4 ARM Cortex-A8......Page 621
16.5 ARM Cortex-M3......Page 629
16.6 Key Terms, Review Questions, and Problems......Page 633
Chapter 17 Parallel Processing......Page 638
17.1 Multiple Processor Organizations......Page 640
17.2 Symmetric Multiprocessors......Page 642
17.3 Cache Coherence and the MESI Protocol......Page 646
17.4 Multithreading and Chip Multiprocessors......Page 653
17.5 Clusters......Page 658
17.6 Nonuniform Memory Access......Page 665
17.7 Cloud Computing......Page 668
17.8 Key Terms, Review Questions, and Problems......Page 675
Chapter 18 Multicore Computers......Page 681
18.1 Hardware Performance Issues......Page 682
18.2 Software Performance Issues......Page 685
18.3 Multicore Organization......Page 690
18.4 Heterogeneous Multicore Organization......Page 692
18.5 Intel Core i7-990X......Page 701
18.6 ARM Cortex-A15 MPCore......Page 702
18.7 IBM zEnterprise EC12 Mainframe......Page 707
18.8 Key Terms, Review Questions, and Problems......Page 710
Chapter 19 General-Purpose Graphic Processing Units......Page 713
19.1 Cuda Basics......Page 714
19.2 GPU versus CPU......Page 716
19.3 GPU Architecture Overview......Page 717
19.4 Intel’s Gen8 GPU......Page 726
19.5 When to Use a GPU as a Coprocessor......Page 729
19.6 Key Terms and Review Questions......Page 731
Chapter 20 Control Unit Operation......Page 732
20.1 Micro-Operations......Page 733
20.2 Control of the Processor......Page 739
20.3 Hardwired Implementation......Page 749
20.4 Key Terms, Review Questions, and Problems......Page 752
Chapter 21 Microprogrammed Control......Page 754
21.1 Basic Concepts......Page 755
21.2 Microinstruction Sequencing......Page 764
21.3 Microinstruction Execution......Page 770
21.4 TI 8800 755......Page 780
21.5 Key Terms, Review Questions, and Problems......Page 791
Appendix A: Projects for Teaching Computer Organization and Architecture......Page 793
A.1 Interactive Simulations......Page 794
A.3 Simulation Projects......Page 796
A.4 Assembly Language Projects......Page 797
A.7 Test Bank......Page 798
Appendix B: Assembly Language and Related Topics......Page 799
B.1 Assembly Language......Page 800
B.2 Assemblers......Page 808
B.3 Loading and Linking......Page 812
B.4 Key Terms, Review Questions, and Problems......Page 820
References......Page 825
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Credits......Page 858