Computer organization and architecture : designing for performance

Cover
Half Title
Title Page
Copyright
Dedication
Contents
Preface
About the Author
Acronyms

Part One Introduction

1.1 Organization and Architecture
1.2 Structure and Function
1.3 The IAS Computer
1.4 Gates, Memory Cells, Chips, and Multichip Modules
1.5 The Evolution of the Intel x86 Architecture
1.6 Embedded Systems
1.7 ARM Architecture
1.8 Key Terms, Review Questions, and Problems

Chapter 2 Performance Concepts
2.1 Designing for Performance
2.2 Multicore, Mics, and GPGPUs
2.3 Two Laws that Provide Insight: Ahmdahl’s Law and Little’s Law
2.4 Basic Measures of Computer Performance
2.5 Calculating the Mean
2.6 Benchmarks and Spec
2.7 Key Terms, Review Questions, and Problems

Part Two The Computer System

3.1 Computer Components
3.2 Computer Function
3.3 Interconnection Structures
3.4 Bus Interconnection
3.5 Point-to-Point Interconnect
3.6 PCI Express
3.7 Key Terms, Review Questions, and Problems

Chapter 4 The Memory Hierarchy: Locality and Performance
4.1 Principle Of Locality
4.2 Characteristics Of Memory Systems
4.3 The Memory Hierarchy
4.4 Performance Modeling Of A Multilevel Memory Hierarchy
4.5 Key Terms, Review Questions, and Problems

Chapter 5 Cache Memory
5.1 Cache Memory Principles
5.2 Elements of Cache Design
5.3 Intel x86 Cache Organization
5.4 The IBM z13 Cache Organization
5.5 Cache Performance Models6
5.6 Key Terms, Review Questions, and Problems

Chapter 6 Internal Memory
6.1 Semiconductor Main Memory
6.2 Error Correction
6.3 DDR DRAM
6.4 Edram
6.5 Flash Memory
6.6 Newer Nonvolatile Solid-State Memory Technologies
6.7 Key Terms, Review Questions, and Problems

Chapter 7 External Memory
7.1 Magnetic Disk
7.2 RAID
7.3 Solid State Drives
7.4 Optical Memory
7.5 Magnetic Tape
7.6 Key Terms, Review Questions, and Problems

Chapter 8 Input/Output
8.1 External Devices
8.2 I/O Modules
8.3 Programmed I/O
8.4 Interrupt-​Driven I/O
8.5 Direct Memory Access
8.6 Direct Cache Access
8.7 I/O Channels and Processors
8.8 External Interconnection Standards
8.9 IBM z13 I/O Structure
8.10 Key Terms, Review Questions, and Problems

Chapter 9 Operating System Support
9.1 Operating System Overview
9.2 Scheduling
9.3 Memory Management
9.4 Intel x86 Memory Management
9.5 ARM Memory Management
9.6 Key Terms, Review Questions, and Problems

Part Three Arithmetic and Logic

10.1 The Decimal System
10.2 Positional Number Systems
10.3 The Binary System
10.4 Converting Between Binary and Decimal
10.5 Hexadecimal Notation
10.6 Key Terms and Problems

Chapter 11 Computer Arithmetic
11.1 The Arithmetic and Logic Unit
11.2 Integer Representation
11.3 Integer Arithmetic
11.4 Floating-Point Representation
11.5 Floating-Point Arithmetic
11.6 Key Terms, Review Questions, and Problems

Chapter 12 Digital Logic
12.1 Boolean Algebra
12.2 Gates
12.3 Combinational Circuits
12.4 Sequential Circuits
12.5 Programmable Logic Devices
12.6 Key Terms and Problems

Part Four Instruction Sets and Assembly Language

13.1 Machine Instruction Characteristics
13.2 Types of Operands
13.3 Intel x86 and ARM Data Types
13.4 Types of Operations
13.5 Intel x86 and ARM Operation Types
13.6 Key Terms, Review Questions, and Problems

Appendix 13A Little-, Big-, and Bi-Endian

Chapter 14 Instruction Sets: Addressing Modes and Formats
14.1 Addressing Modes
14.2 x86 and ARM Addressing Modes
14.3 Instruction Formats
14.4 x86 and ARM Instruction Formats
14.5 Key Terms, Review Questions, and Problems

Chapter 15 Assembly Language and Related Topics
15.1 Assembly Language Concepts
15.2 Motivation For Assembly Language Programming
15.3 Assembly Language Elements
15.4 EXAMPLES
15.5 Types of assemblers
15.6 Assemblers
15.7 Loading and Linking
15.8 Key Terms, Review Questions, and Problems

Part Five The Central Processing Unit

16.1 Processor Organization
16.2 Register Organization
16.3 Instruction Cycle
16.4 Instruction Pipelining
16.5 Processor Organization for Pipelining
16.6 The x86 Processor Family
16.7 The ARM Processor
16.8 Key Terms, Review Questions, and Problems

Chapter 17 Reduced Instruction Set Computers
17.1 Instruction Execution Characteristics
17.2 The Use of a Large Register File
17.3 Compiler-​Based Register Optimization
17.4 Reduced Instruction Set Architecture
17.5 Risc Pipelining
17.6 MIPS R4000
17.7 SPARC
17.8 Processor Organization For Pipelining
17.9 CISC, RISC, And Contemporary Systems
17.10 Key Terms, Review Questions, and Problems

Chapter 18 Instruction-Level Parallelism and Superscalar Processors
18.1 Overview
18.2 Design Issues
18.3 Intel Core Microarchitecture
18.4 ARM Cortex-A8
18.5 ARM Cortex-M3
18.6 Key Terms, Review Questions, and Problems

Chapter 19 Control Unit Operation and Microprogrammed Control
19.1 Micro-​Operations
19.2 Control of the Processor
19.3 Hardwired Implementation
19.4 Microprogrammed Control
19.5 Key Terms, Review Questions, and Problems

Part Six Parallel Organization

20.1 Multiple Processor Organizations
20.2 Symmetric Multiprocessors
20.3 Cache Coherence and the MESI Protocol
20.4 Multithreading and Chip Multiprocessors
20.5 Clusters
20.6 Nonuniform Memory Access
20.7 Key Terms, Review Questions, and Problems

Chapter 21 Multicore Computers
21.1 Hardware Performance Issues
21.2 Software Performance Issues
21.3 Multicore Organization
21.4 Heterogeneous Multicore Organization
21.5 INTEL Core i7-5960X
21.6 ARM Cortex-​A15 MPCore
21.7 IBM z13 Mainframe
21.8 Key Terms, Review Questions, and Problems

Appendix A System Buses
A.1 Bus Structure
A.2 Multiple-Bus Hierarchies
A.3 Elements of Bus Design

Appendix B Victim Cache Strategies
B.1 Victim Cache
B.2 Selective Victim Cache

Appendix C Interleaved Memory

Appendix D The International Reference Alphabet

Appendix E Stacks
E.1 Stacks
E.2 Stack Implementation
E.3 Expression Evaluation

Appendix F Recursive Procedures
F.1 Recursion
F.2 Activation Tree Representation
F.3 Stack Implementation
F.4 Recursion And Iteration

Appendix G Additional Instruction Pipeline Topics
G.1 Pipeline Reservation Tables
G.2 Reorder Buffers
G.3 Tomasulo’s Algorithm
G.4 Scoreboarding

Glossary
References
Supplemental Materials
Index